mx6cuboxi: Introduce multi-SoC support
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite, mx6dual and mx6quad. Add support for the different SoC/memory sizes combinations. DDR initialization values were extracted from Solid-run internal U-boot. Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
cfdcc5f781
commit
8cb6817e3a
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@ -175,7 +175,7 @@ int checkboard(void)
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#ifdef CONFIG_SPL_BUILD
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#include <asm/arch/mx6-ddr.h>
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static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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@ -204,7 +204,36 @@ static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm7 = 0x00020030,
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};
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static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
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.dram_sdclk_0 = 0x00000028,
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.dram_sdclk_1 = 0x00000028,
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.dram_cas = 0x00000028,
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.dram_ras = 0x00000028,
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.dram_reset = 0x000c0028,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x00003030,
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.dram_sdodt1 = 0x00003030,
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.dram_sdqs0 = 0x00000028,
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.dram_sdqs1 = 0x00000028,
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.dram_sdqs2 = 0x00000028,
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.dram_sdqs3 = 0x00000028,
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.dram_sdqs4 = 0x00000028,
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.dram_sdqs5 = 0x00000028,
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.dram_sdqs6 = 0x00000028,
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.dram_sdqs7 = 0x00000028,
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.dram_dqm0 = 0x00000028,
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.dram_dqm1 = 0x00000028,
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.dram_dqm2 = 0x00000028,
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.dram_dqm3 = 0x00000028,
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.dram_dqm4 = 0x00000028,
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.dram_dqm5 = 0x00000028,
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.dram_dqm6 = 0x00000028,
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.dram_dqm7 = 0x00000028,
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};
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static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
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.grp_ddr_type = 0x000C0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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@ -221,7 +250,25 @@ static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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.grp_b7ds = 0x00000030,
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};
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static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x00000028,
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.grp_ctlds = 0x00000028,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000028,
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.grp_b1ds = 0x00000028,
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.grp_b2ds = 0x00000028,
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.grp_b3ds = 0x00000028,
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.grp_b4ds = 0x00000028,
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.grp_b5ds = 0x00000028,
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.grp_b6ds = 0x00000028,
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.grp_b7ds = 0x00000028,
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};
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/* microSOM with Dual processor and 1GB memory */
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static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00000000,
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.p0_mpwldectrl1 = 0x00000000,
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.p1_mpwldectrl0 = 0x00000000,
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@ -236,7 +283,49 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p1_mpwrdlctl = 0x422a423c,
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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/* microSOM with Quad processor and 2GB memory */
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static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00000000,
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.p0_mpwldectrl1 = 0x00000000,
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.p1_mpwldectrl0 = 0x00000000,
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.p1_mpwldectrl1 = 0x00000000,
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.p0_mpdgctrl0 = 0x0314031c,
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.p0_mpdgctrl1 = 0x023e0304,
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.p1_mpdgctrl0 = 0x03240330,
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.p1_mpdgctrl1 = 0x03180260,
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.p0_mprddlctl = 0x3630323c,
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.p1_mprddlctl = 0x3436283a,
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.p0_mpwrdlctl = 0x36344038,
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.p1_mpwrdlctl = 0x422a423c,
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};
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/* microSOM with Solo processor and 512MB memory */
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static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
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.p0_mpwldectrl0 = 0x0045004D,
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.p0_mpwldectrl1 = 0x003A0047,
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.p0_mpdgctrl0 = 0x023C0224,
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.p0_mpdgctrl1 = 0x02000220,
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.p0_mprddlctl = 0x44444846,
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.p0_mpwrdlctl = 0x32343032,
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};
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/* microSOM with Dual lite processor and 1GB memory */
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static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
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.p0_mpwldectrl0 = 0x0045004D,
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.p0_mpwldectrl1 = 0x003A0047,
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.p1_mpwldectrl0 = 0x001F001F,
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.p1_mpwldectrl1 = 0x00210035,
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.p0_mpdgctrl0 = 0x023C0224,
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.p0_mpdgctrl1 = 0x02000220,
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.p1_mpdgctrl0 = 0x02200220,
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.p1_mpdgctrl1 = 0x02000220,
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.p0_mprddlctl = 0x44444846,
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.p1_mprddlctl = 0x4042463C,
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.p0_mpwrdlctl = 0x32343032,
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.p1_mpwrdlctl = 0x36363430,
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};
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static struct mx6_ddr3_cfg mem_ddr_2g = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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@ -250,6 +339,19 @@ static struct mx6_ddr3_cfg mem_ddr = {
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.SRT = 1,
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};
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static struct mx6_ddr3_cfg mem_ddr_4g = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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@ -278,11 +380,11 @@ static void gpr_init(void)
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* This section requires the differentiation between Solidrun mx6 boards, but
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* for now, it will configure only for the mx6dual hummingboard version.
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*/
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static void spl_dram_init(void)
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static void spl_dram_init(int width)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus: 0=16, 1=32, 2=64 */
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.dsize = 2,
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.dsize = width / 32,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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.ncs = 1, /* single chip select */
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@ -297,8 +399,19 @@ static void spl_dram_init(void)
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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};
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mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
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if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))
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mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
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else
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mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
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if (is_cpu_type(MXC_CPU_MX6D))
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mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
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else if (is_cpu_type(MXC_CPU_MX6Q))
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mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
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else if (is_cpu_type(MXC_CPU_MX6DL))
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mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
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else if (is_cpu_type(MXC_CPU_MX6SOLO))
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mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
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}
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void board_init_f(ulong dummy)
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@ -319,7 +432,10 @@ void board_init_f(ulong dummy)
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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if (is_cpu_type(MXC_CPU_MX6SOLO))
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spl_dram_init(32);
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else
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spl_dram_init(64);
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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