sunxi: Add basic A33 basic support
Enable full support for the A33 SoC including display, otg-usb, etc. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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@ -39,5 +39,6 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
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obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
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obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
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obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
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obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
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obj-y += fel_utils.o
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endif
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@ -66,6 +66,8 @@ int print_cpuinfo(void)
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puts("CPU: Allwinner A20 (SUN7I)\n");
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#elif defined CONFIG_MACH_SUN8I_A23
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puts("CPU: Allwinner A23 (SUN8I)\n");
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#elif defined CONFIG_MACH_SUN8I_A33
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puts("CPU: Allwinner A33 (SUN8I)\n");
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#else
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#warning Please update cpu_info.c with correct CPU information
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puts("CPU: SUNXI Family\n");
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@ -28,7 +28,11 @@
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#endif
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#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
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#ifdef CONFIG_MACH_SUN8I_A33
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#define SUNXI_USB_CSR 0x410
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#else
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#define SUNXI_USB_CSR 0x404
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#endif
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#define SUNXI_USB_PASSBY_EN 1
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#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
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@ -103,6 +107,11 @@ static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr,
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int j = 0, usbc_bit = 0;
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void *dest = sunxi_usbc_get_io_base(0) + SUNXI_USB_CSR;
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#ifdef CONFIG_MACH_SUN8I_A33
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/* CSR needs to be explicitly initialized to 0 on A33 */
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writel(0, dest);
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#endif
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usbc_bit = 1 << (sunxi_usbc->id * 2);
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for (j = 0; j < len; j++) {
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/* set the bit address to be written */
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@ -52,6 +52,12 @@ config MACH_SUN8I_A23
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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config MACH_SUN8I_A33
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bool "sun8i (Allwinner A33)"
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select CPU_V7
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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endchoice
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# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
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@ -458,8 +458,13 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
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static inline u8 musb_read_configdata(void __iomem *mbase)
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{
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#ifdef CONFIG_MACH_SUN8I_A33
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/* <Sigh> allwinner saves a reg, and we need to hardcode this */
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return 0xde;
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#else
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musb_writeb(mbase, MUSB_INDEX, 0);
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return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
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#endif
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}
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static inline u16 musb_read_hwvers(void __iomem *mbase)
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@ -947,6 +947,9 @@ static void sunxi_drc_init(void)
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* On sun6i the drc must be clocked even when in pass-through mode */
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#ifdef CONFIG_MACH_SUN8I_A33
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setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
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#endif
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setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
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clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
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#endif
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