rockchip: clk: Add support for clocks needed by the displays
The displays need to use NPLL and also select some new peripheral clocks. Add support for these to the clock driver. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
parent
009741fbae
commit
830a608170
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@ -235,6 +235,124 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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#define VCO_MAX_KHZ 2200000
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#define VCO_MIN_KHZ 440000
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#define FREF_MAX_KHZ 2200000
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#define FREF_MIN_KHZ 269
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static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
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{
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uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
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uint fref_khz;
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uint diff_khz, best_diff_khz;
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const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
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uint vco_khz;
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uint no = 1;
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uint freq_khz = freq_hz / 1000;
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if (!freq_hz) {
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printf("%s: the frequency can not be 0 Hz\n", __func__);
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return -EINVAL;
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}
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no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
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if (ext_div) {
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*ext_div = DIV_ROUND_UP(no, max_no);
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no = DIV_ROUND_UP(no, *ext_div);
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}
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/* only even divisors (and 1) are supported */
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if (no > 1)
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no = DIV_ROUND_UP(no, 2) * 2;
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vco_khz = freq_khz * no;
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if (ext_div)
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vco_khz *= *ext_div;
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if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
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printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
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__func__, freq_hz);
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return -1;
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}
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div->no = no;
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best_diff_khz = vco_khz;
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for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
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fref_khz = ref_khz / nr;
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if (fref_khz < FREF_MIN_KHZ)
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break;
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if (fref_khz > FREF_MAX_KHZ)
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continue;
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nf = vco_khz / fref_khz;
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if (nf >= max_nf)
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continue;
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diff_khz = vco_khz - nf * fref_khz;
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if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
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nf++;
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diff_khz = fref_khz - diff_khz;
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}
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if (diff_khz >= best_diff_khz)
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continue;
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best_diff_khz = diff_khz;
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div->nr = nr;
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div->nf = nf;
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}
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if (best_diff_khz > 4 * 1000) {
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printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
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__func__, freq_hz, best_diff_khz * 1000);
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return -EINVAL;
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}
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return 0;
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}
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static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
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int periph, unsigned int rate_hz)
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{
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struct pll_div npll_config = {0};
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u32 lcdc_div;
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int ret;
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ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
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if (ret)
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return ret;
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rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
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NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
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rkclk_set_pll(cru, CLK_NEW, &npll_config);
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/* waiting for pll lock */
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while (1) {
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if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
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break;
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udelay(1);
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}
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rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
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NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
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/* vop dclk source clk: npll,dclk_div: 1 */
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switch (periph) {
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case DCLK_VOP0:
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rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
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(lcdc_div - 1) << 8 | 2 << 0);
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break;
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case DCLK_VOP1:
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rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
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(lcdc_div - 1) << 8 | 2 << 6);
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break;
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
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{
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@ -559,6 +677,7 @@ static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
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static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
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{
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struct rk3288_clk_priv *priv = dev_get_priv(dev);
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struct rk3288_cru *cru = priv->cru;
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struct udevice *gclk;
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ulong new_rate, gclk_rate;
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int ret;
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@ -571,15 +690,62 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
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case HCLK_EMMC:
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case HCLK_SDMMC:
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case HCLK_SDIO0:
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new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, periph,
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rate);
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new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
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break;
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case SCLK_SPI0:
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case SCLK_SPI1:
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case SCLK_SPI2:
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new_rate = rockchip_spi_set_clk(priv->cru, gclk_rate, periph,
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rate);
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new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
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break;
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#ifndef CONFIG_SPL_BUILD
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case DCLK_VOP0:
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case DCLK_VOP1:
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new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
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break;
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case SCLK_EDP_24M:
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/* clk_edp_24M source: 24M */
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rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
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/* rst edp */
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rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
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udelay(1);
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rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
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new_rate = rate;
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break;
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case ACLK_VOP0:
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case ACLK_VOP1: {
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u32 div;
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/* vop aclk source clk: cpll */
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div = CPLL_HZ / rate;
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assert((div - 1 < 64) && (div * rate == CPLL_HZ));
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switch (periph) {
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case ACLK_VOP0:
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rk_clrsetreg(&cru->cru_clksel_con[31],
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3 << 6 | 0x1f << 0,
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0 << 6 | (div - 1) << 0);
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break;
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case ACLK_VOP1:
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rk_clrsetreg(&cru->cru_clksel_con[31],
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3 << 14 | 0x1f << 8,
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0 << 14 | (div - 1) << 8);
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break;
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}
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new_rate = rate;
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break;
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}
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case PCLK_HDMI_CTRL:
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/* enable pclk hdmi ctrl */
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rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
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/* software reset hdmi */
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rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
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udelay(1);
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rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
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new_rate = rate;
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break;
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#endif
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default:
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return -ENOENT;
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}
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