powerpc: mpc85xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig option
Move the macro to Kconfig SYS_FSL_NUM_LAWS. Signed-off-by: York Sun <york.sun@nxp.com>
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York Sun
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f4325b47a8
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8303acbce8
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@ -569,6 +569,54 @@ config SYS_CCSRBAR_DEFAULT
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if changed by pre-boot regime. The value here must match
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the current value in SoC. If not sure, do not change.
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config SYS_FSL_NUM_LAWS
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int "Number of local access windows"
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depends on FSL_LAW
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default 32 if ARCH_B4420 || \
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ARCH_B4860 || \
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ARCH_P2041 || \
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ARCH_P3041 || \
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ARCH_P4080 || \
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ARCH_P5020 || \
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ARCH_P5040 || \
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ARCH_T2080 || \
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ARCH_T2081 || \
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ARCH_T4160 || \
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ARCH_T4240
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default 16 if ARCH_T1013 || \
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ARCH_T1014 || \
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ARCH_T1020 || \
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ARCH_T1022 || \
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ARCH_T1023 || \
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ARCH_T1024 || \
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ARCH_T1040 || \
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ARCH_T1042
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default 12 if ARCH_BSC9131 || \
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ARCH_BSC9132 || \
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ARCH_C29X || \
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ARCH_MPC8536 || \
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ARCH_MPC8572 || \
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ARCH_P1010 || \
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ARCH_P1011 || \
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ARCH_P1020 || \
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ARCH_P1021 || \
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ARCH_P1022 || \
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ARCH_P1023 || \
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ARCH_P1024 || \
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ARCH_P1025 || \
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ARCH_P2020
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default 10 if ARCH_MPC8544 || \
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ARCH_MPC8548 || \
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ARCH_MPC8568 || \
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ARCH_MPC8569
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default 8 if ARCH_MPC8540 || \
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ARCH_MPC8541 || \
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ARCH_MPC8555 || \
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ARCH_MPC8560
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help
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Number of local access windows. This is fixed per SoC.
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If not sure, do not change.
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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@ -32,30 +32,25 @@
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#endif
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#if defined(CONFIG_ARCH_MPC8536)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_MPC8540)
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#elif defined(CONFIG_ARCH_MPC8541)
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#elif defined(CONFIG_ARCH_MPC8544)
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_MPC8548)
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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@ -72,16 +67,13 @@
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
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#elif defined(CONFIG_ARCH_MPC8555)
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#elif defined(CONFIG_ARCH_MPC8560)
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#elif defined(CONFIG_ARCH_MPC8568)
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x10000UL
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@ -94,7 +86,6 @@
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_ARCH_MPC8569)
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x20000UL
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#define MAX_QE_RISC 4
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@ -108,7 +99,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_MPC8572)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_DDR_115
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@ -118,7 +108,6 @@
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#elif defined(CONFIG_ARCH_P1010)
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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@ -144,7 +133,6 @@
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/* P1011 is single core version of P1020 */
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#elif defined(CONFIG_ARCH_P1011)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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@ -156,7 +144,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_P1020)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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@ -170,7 +157,6 @@
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#endif
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#elif defined(CONFIG_ARCH_P1021)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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@ -185,7 +171,6 @@
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#elif defined(CONFIG_ARCH_P1022)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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@ -198,7 +183,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A004477
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#elif defined(CONFIG_ARCH_P1023)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 2
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@ -215,7 +199,6 @@
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/* P1024 is lower end variant of P1020 */
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#elif defined(CONFIG_ARCH_P1024)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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@ -228,7 +211,6 @@
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/* P1025 is lower end variant of P1021 */
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#elif defined(CONFIG_ARCH_P1025)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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@ -243,7 +225,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_P2020)
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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@ -262,7 +243,6 @@
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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@ -298,7 +278,6 @@
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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@ -336,7 +315,6 @@
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 2
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#define CONFIG_SYS_NUM_FM1_DTSEC 4
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@ -386,7 +364,6 @@
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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@ -420,7 +397,6 @@
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 2
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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@ -449,7 +425,6 @@
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#elif defined(CONFIG_ARCH_BSC9131)
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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@ -467,7 +442,6 @@
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#elif defined(CONFIG_ARCH_BSC9132)
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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@ -515,7 +489,6 @@
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#endif
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#endif
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SRDS_2
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#define CONFIG_SYS_FSL_SRDS_3
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@ -557,7 +530,6 @@
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#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
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#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
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#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SRDS_2
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#define CONFIG_SYS_MAPLE
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@ -625,7 +597,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#endif
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
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#define CONFIG_SYS_FSL_NUM_LAWS 16
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SEC_COMPAT 5
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#define CONFIG_SYS_NUM_FMAN 1
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@ -671,7 +642,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#endif
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#define CONFIG_SYS_FSL_NUM_CC_PLL 2
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
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#define CONFIG_SYS_FSL_NUM_LAWS 16
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SEC_COMPAT 5
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#define CONFIG_SYS_NUM_FMAN 1
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@ -709,7 +679,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_QMAN_V3
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
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@ -756,7 +725,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#elif defined(CONFIG_ARCH_C29X)
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2_1
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#define CONFIG_SYS_FSL_SEC_COMPAT 6
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