Coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
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56
CREDITS
56
CREDITS
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@ -147,6 +147,11 @@ N: Daniel Engstr
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E: daniel@omicron.se
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E: daniel@omicron.se
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D: x86 port, Support for sc520_cdp board
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D: x86 port, Support for sc520_cdp board
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N: Hayden Fraser
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E: Hayden.Fraser@freescale.com
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D: Support for ColdFire MCF5253
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W: www.freescale.com
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N: Dr. Wolfgang Grandegger
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N: Dr. Wolfgang Grandegger
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E: wg@denx.de
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E: wg@denx.de
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D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
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D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
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@ -283,6 +288,11 @@ E: team@leox.org
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D: Support for LEOX boards, DS164x RTC
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D: Support for LEOX boards, DS164x RTC
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W: http://www.leox.org
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W: http://www.leox.org
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N: TsiChung Liew
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E: Tsi-Chung.Liew@freescale.com
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D: Support for ColdFire MCF523x, MCF532x, MCF5445x
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W: www.freescale.com
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N: Leif Lindholm
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N: Leif Lindholm
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E: leif.lindholm@i3micro.com
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E: leif.lindholm@i3micro.com
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D: Support for AMD dbau1550 board.
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D: Support for AMD dbau1550 board.
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@ -297,6 +307,11 @@ N: Raymond Lo
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E: lo@routefree.com
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E: lo@routefree.com
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D: Support for DOS partitions
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D: Support for DOS partitions
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N: James MacAulay
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E: james.macaulay@amirix.com
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D: Suppport for Amirix AP1000
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W: www.amirix.com
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N: Dan Malek
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N: Dan Malek
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E: dan@embeddedalley.com
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E: dan@embeddedalley.com
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D: FADSROM, the grandfather of all of this
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D: FADSROM, the grandfather of all of this
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@ -372,8 +387,9 @@ D: Support for the Wind River sbc405, sbc8240 board
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W: http://www.windriver.com
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W: http://www.windriver.com
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N: Stefan Roese
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N: Stefan Roese
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E: stefan.roese@esd-electronics.com
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E: sr@denx.de
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D: AMCC PPC401/403/405GP Support; Windows environment support
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D: AMCC PPC4xx Support
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W: http://www.denx.de
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N: Erwin Rol
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N: Erwin Rol
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E: erwin@muffin.org
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E: erwin@muffin.org
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@ -407,6 +423,11 @@ N: Art Shipkowski
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E: art@videon-central.com
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E: art@videon-central.com
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D: Support for NetSilicon NS7520
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D: Support for NetSilicon NS7520
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N: Michal Simek
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E: monstr@monstr.eu
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D: Support for Microblaze, ML401, XUPV2P board
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W: www.monstr.eu
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N: Yasushi Shoji
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N: Yasushi Shoji
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E: yashi@atmark-techno.com
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E: yashi@atmark-techno.com
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D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
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D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
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@ -420,6 +441,11 @@ E: andrea.scian@dave-tech.it
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D: Port to B2 board
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D: Port to B2 board
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W: www.dave-tech.it
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W: www.dave-tech.it
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N: Timur Tabi
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E: timur@freescale.com
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D: Support for MPC8349E-mITX
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W: www.freescale.com
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N: Rob Taylor
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N: Rob Taylor
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E: robt@flyingpig.com
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E: robt@flyingpig.com
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D: Port to MBX860T and Sandpoint8240
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D: Port to MBX860T and Sandpoint8240
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@ -473,29 +499,3 @@ N: Alex Zuepke
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E: azu@sysgo.de
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E: azu@sysgo.de
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D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
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D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
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W: www.elinos.com
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W: www.elinos.com
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N: James MacAulay
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E: james.macaulay@amirix.com
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D: Suppport for Amirix AP1000
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W: www.amirix.com
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N: Timur Tabi
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E: timur@freescale.com
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D: Support for MPC8349E-mITX
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W: www.freescale.com
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N: Michal Simek
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E: monstr@monstr.eu
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D: Support for Microblaze, ML401, XUPV2P board
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W: www.monstr.eu
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N: TsiChung Liew
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E: Tsi-Chung.Liew@freescale.com
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D: Support for ColdFire MCF523x, MCF532x, MCF5445x
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W: www.freescale.com
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N: Hayden Fraser
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E: Hayden.Fraser@freescale.com
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D: Support for ColdFire MCF5253
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W: www.freescale.com
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@ -111,4 +111,3 @@ int testdram (void) {
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return (0);
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return (0);
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}
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}
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@ -130,4 +130,3 @@ void ide_set_reset(int idereset)
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}
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}
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}
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}
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#endif /* CONFIG_CMD_IDE */
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#endif /* CONFIG_CMD_IDE */
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@ -162,4 +162,3 @@ void pci_init_board(void)
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pci_mcf5445x_init(&hose);
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pci_mcf5445x_init(&hose);
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}
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}
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#endif /* CONFIG_PCI */
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#endif /* CONFIG_PCI */
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@ -127,19 +127,19 @@ int cpu_init_r(void)
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void uart_port_conf(void)
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void uart_port_conf(void)
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{
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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/* Setup Ports: */
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switch (CFG_UART_PORT) {
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switch (CFG_UART_PORT) {
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case 0:
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case 0:
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gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
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gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
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break;
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break;
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case 1:
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case 1:
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gpio->par_uart =
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gpio->par_uart =
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(GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
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(GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
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break;
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break;
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case 2:
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case 2:
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gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
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gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
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break;
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break;
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}
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}
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}
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}
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@ -41,8 +41,9 @@ int get_clocks(void)
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pll->syncr = PLL_SYNCR_MFD(1);
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pll->syncr = PLL_SYNCR_MFD(1);
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while (!(pll->synsr & PLL_SYNSR_LOCK));
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while (!(pll->synsr & PLL_SYNSR_LOCK));
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gd->bus_clk = CFG_CLK;
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gd->bus_clk = CFG_CLK;
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gd->cpu_clk = (gd->bus_clk * 2);
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gd->cpu_clk = (gd->bus_clk * 2);
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return (0);
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return (0);
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}
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}
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@ -63,7 +63,7 @@ void cpu_init_f(void)
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mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
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mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
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mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
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mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
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/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
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/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
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/*
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/*
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* Setup chip selects...
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* Setup chip selects...
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@ -18,14 +18,14 @@ Created 06/05/2007
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SDR: 0x00000000-0x00ffffff
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SDR: 0x00000000-0x00ffffff
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SRAM0: 0x20010000-0x20017fff
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SRAM0: 0x20010000-0x20017fff
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SRAM1: 0x20000000-0x2000ffff
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SRAM1: 0x20000000-0x2000ffff
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MBAR1: 0x10000000-0x4fffffff
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MBAR1: 0x10000000-0x4fffffff
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MBAR2: 0x80000000-0xCfffffff
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MBAR2: 0x80000000-0xCfffffff
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Flash: 0xffe00000-0xffffffff
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Flash: 0xffe00000-0xffffffff
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3. DEFINITIONS AND COMPILATION
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3. DEFINITIONS AND COMPILATION
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==============================
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==============================
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3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
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3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
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CONFIG_MCF52x2 Processor family
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CONFIG_MCF52x2 Processor family
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CONFIG_MCF5253 MCF5253 specific
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CONFIG_MCF5253 MCF5253 specific
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CONFIG_M5253EVBE Amadeus Plus board specific
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CONFIG_M5253EVBE Amadeus Plus board specific
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CFG_CLK Define Amadeus Plus CPU Clock
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CFG_CLK Define Amadeus Plus CPU Clock
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@ -192,4 +192,3 @@
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#define CFG_GPIO1_LED 0x00400000 /* user led */
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#define CFG_GPIO1_LED 0x00400000 /* user led */
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#endif /* M5249 */
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#endif /* M5249 */
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@ -210,4 +210,3 @@
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#define CFG_GPIO1_LED 0x00400000 /* user led */
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#define CFG_GPIO1_LED 0x00400000 /* user led */
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#endif /* _M5253EVB_H */
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#endif /* _M5253EVB_H */
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*/
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*/
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asm("movel %%a7, %%d0\n"
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asm("movel %%a7, %%d0\n"
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"movel %%d0, %0\n": "=d"(sp): :"%d0");
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"movel %%d0, %0\n": "=d"(sp): :"%d0");
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debug("## Current stack ends at 0x%08lX ", sp);
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debug("## Current stack ends at 0x%08lX ", sp);
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sp -= 2048; /* just to be sure */
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sp -= 2048; /* just to be sure */
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if (sp > CFG_BOOTMAPSZ)
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if (sp > CFG_BOOTMAPSZ)
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*/
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*/
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asm("movel %%a7, %%d0\n"
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asm("movel %%a7, %%d0\n"
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"movel %%d0, %0\n": "=d"(nsp): :"%d0");
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"movel %%d0, %0\n": "=d"(nsp): :"%d0");
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nsp -= 2048; /* just to be sure */
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nsp -= 2048; /* just to be sure */
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nsp &= ~0xF;
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nsp &= ~0xF;
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if (nsp > initrd_high) /* limit as specified */
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if (nsp > initrd_high) /* limit as specified */
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