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uboot
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Merge git://www.denx.de/git/u-boot 

Conflicts:

	drivers/Makefile
This commit is contained in:
Nobuhiro Iwamatsu 2007-11-29 00:56:37 +09:00
parent eda3e1e661 f92edbd8a0
commit 7fc792895b
237 changed files with 7846 additions and 1651 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
.gitignore vendored Normal file
View File

@ -0,0 +1,13 @@
*.orig
*.a
*.o
*.depend
System.map
/u-boot
/u-boot.map
/u-boot.bin
/u-boot.srec
/LOG
/errlog
/reloc_off

1891
CHANGELOG
View File

File diff suppressed because it is too large Load Diff

3
MAKEALL
View File

@ -301,10 +301,12 @@ LIST_83xx=" \
MPC8313ERDB_66 \
MPC8323ERDB \
MPC832XEMDS \
MPC832XEMDS_ATM \
MPC8349EMDS \
MPC8349ITX \
MPC8349ITXGP \
MPC8360EMDS \
MPC8360EMDS_ATM \
sbc8349 \
TQM834x \
"
@ -552,6 +554,7 @@ LIST_mips5kc_el=""
LIST_au1xx0_el=" \
dbau1550_el \
pb1000 \
"
LIST_mips_el=" \

45
Makefile
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2000-2006
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -24,7 +24,7 @@
VERSION = 1
PATCHLEVEL = 3
SUBLEVEL = 0
EXTRAVERSION = -rc2
EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
@ -214,6 +214,7 @@ LIBS += drivers/libdrivers.a
LIBS += drivers/bios_emulator/libatibiosemu.a
LIBS += drivers/nand/libnand.a
LIBS += drivers/nand_legacy/libnand_legacy.a
LIBS += drivers/onenand/libonenand.a
LIBS += drivers/net/libnet.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
@ -395,7 +396,7 @@ BC3450_config: unconfig
cpci5200_config: unconfig
@$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd
hmi1001_config: unconfig
hmi1001_config: unconfig
@$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001
Lite5200_config \
@ -437,7 +438,7 @@ icecube_5100_config: unconfig
}
@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
jupiter_config: unconfig
jupiter_config: unconfig
@$(MKCONFIG) jupiter ppc mpc5xxx jupiter
v38b_config: unconfig
@ -642,9 +643,9 @@ TQM5200_STK100_config: unconfig
{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
}
@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
uc101_config: unconfig
uc101_config: unconfig
@$(MKCONFIG) uc101 ppc mpc5xxx uc101
motionpro_config: unconfig
motionpro_config: unconfig
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
@ -932,7 +933,7 @@ RPXlite_DW_NVRAM_config \
RPXlite_DW_NVRAM_64_config \
RPXlite_DW_NVRAM_LCD_config \
RPXlite_DW_NVRAM_64_LCD_config \
RPXlite_DW_config: unconfig
RPXlite_DW_config: unconfig
@mkdir -p $(obj)include
@ >$(obj)include/config.h
@[ -z "$(findstring _64,$@)" ] || \
@ -1735,9 +1736,13 @@ M54455EVB_i66_config : unconfig
>include/config.h ; \
if [ "$${FLASH}" == "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
echo "... with INTEL boot..." ; \
else \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
echo "... with ATMEL boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
@ -1768,7 +1773,8 @@ MPC8323ERDB_config: unconfig
MPC832XEMDS_config \
MPC832XEMDS_HOST_33_config \
MPC832XEMDS_HOST_66_config \
MPC832XEMDS_SLAVE_config: unconfig
MPC832XEMDS_SLAVE_config \
MPC832XEMDS_ATM_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
@ -1783,10 +1789,17 @@ MPC832XEMDS_SLAVE_config: unconfig
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _ATM_,$@)" ] ; then \
echo -n "...ATM..." ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
@ -1810,7 +1823,8 @@ MPC8349ITXGP_config: unconfig
MPC8360EMDS_config \
MPC8360EMDS_HOST_33_config \
MPC8360EMDS_HOST_66_config \
MPC8360EMDS_SLAVE_config: unconfig
MPC8360EMDS_SLAVE_config \
MPC8360EMDS_ATM_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
@ -1825,10 +1839,17 @@ MPC8360EMDS_SLAVE_config: unconfig
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _ATM_,$@)" ] ; then \
echo -n "...ATM..." ; \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
@ -1987,13 +2008,13 @@ AmigaOneG3SE_config: unconfig
BAB7xx_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx bab7xx eltec
CPCI750_config: unconfig
CPCI750_config: unconfig
@$(MKCONFIG) CPCI750 ppc 74xx_7xx cpci750 esd
DB64360_config: unconfig
DB64360_config: unconfig
@$(MKCONFIG) DB64360 ppc 74xx_7xx db64360 Marvell
DB64460_config: unconfig
DB64460_config: unconfig
@$(MKCONFIG) DB64460 ppc 74xx_7xx db64460 Marvell
ELPPC_config: unconfig

2
README
View File

@ -2123,7 +2123,7 @@ to save the current settings.
to be a good choice since it makes it far enough from the
start of the data area as well as from the stack pointer.
Please note that the environment is read-only as long as the monitor
Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_r()
until then to read environment variables.

2
blackfin_config.mk
View File

@ -21,4 +21,4 @@
# MA 02111-1307 USA
#
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__BLACKFIN__

1
board/ads5121/u-boot.lds
View File

@ -51,6 +51,7 @@ SECTIONS
{
cpu/mpc512x/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)

17
board/amcc/luan/luan.c
View File

@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
************************************************************************/
int board_early_init_f(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
@ -66,8 +64,6 @@ int board_early_init_f(void)
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
return 0;
}
@ -79,7 +75,18 @@ int board_early_init_f(void)
int misc_init_r(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
/* set modes of operation */
x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
/* put Ethernet+PHY in reset */
x->ethuart &= ~EPLD2_RESET_ETH_N;
udelay(10000);
/* take Ethernet+PHY out of reset */
x->ethuart |= EPLD2_RESET_ETH_N;
return 0;
}

17
board/amcc/sequoia/cmd_sequoia.c
View File

@ -25,6 +25,7 @@
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <asm/io.h>
/*
* There are 2 versions of production Sequoia & Rainier platforms.
@ -39,7 +40,7 @@
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
* the only value affected for a 66MHz PCI and simply needs a +0x10.
* the only value affected for a 33MHz PCI and simply needs a | 0x08.
*/
#define NAND_COMPATIBLE 0x01
@ -56,6 +57,7 @@ static char *config_labels[] = {
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
@ -96,6 +98,11 @@ static u8 boot_configs[][17] = {
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
@ -200,8 +207,12 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
/* check CPLD register +5 for PCI 66MHz flag */
if (in8(CFG_BCSR_BASE + 5) & 0x01)
buf[5] += 0x10;
if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
/*
* PLB-to-PCI divisor = 3 for 33MHz sync PCI
* instead of 2 for 66MHz systems
*/
buf[5] |= 0x08;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);

7
board/amcc/sequoia/sequoia.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2006
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
@ -24,6 +24,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <ppc440.h>
DECLARE_GLOBAL_DATA_PTR;
@ -362,8 +363,8 @@ int checkboard(void)
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
rev = in8(CFG_BCSR_BASE + 0);
val = in8(CFG_BCSR_BASE + 5) & 0x01;
rev = in_8((void *)(CFG_BCSR_BASE + 0));
val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {

7
board/amcc/yosemite/yosemite.c
View File

@ -1,4 +1,6 @@
/*
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -22,6 +24,7 @@
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
@ -181,8 +184,8 @@ int checkboard(void)
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
#endif
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
rev = in_8((void *)(CFG_BCSR_BASE + 0));
val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {

2
board/at91rm9200dk/led.c
View File

@ -66,7 +66,7 @@ void red_LED_off(void)
}
void LED_init (void)
void coloured_LED_init (void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
AT91PS_PMC PMC = AT91C_BASE_PMC;

4
board/atmel/atstk1000/flash.c
View File

@ -55,10 +55,6 @@ unsigned long flash_init(void)
unsigned long addr;
unsigned int i;
gd->bd->bi_flashstart = CFG_FLASH_BASE;
gd->bd->bi_flashsize = CFG_FLASH_SIZE;
gd->bd->bi_flashoffset = _edata - _text;
flash_info[0].size = CFG_FLASH_SIZE;
flash_info[0].sector_count = 135;

23
board/cds/common/ft_board.c
View File

@ -37,17 +37,24 @@ static void cds_pci_fixup(void *blob)
map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
len /= sizeof(u32);
if (!map)
map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
slot = get_pci_slot();
if (map) {
len /= sizeof(u32);
for (i=0;i<len;i+=7) {
/* We rotate the interrupt pins so that the mapping
* changes depending on the slot the carrier card is in.
*/
map[3] = ((map[3] + slot - 2) % 4) + 1;
slot = get_pci_slot();
map+=7;
for (i=0;i<len;i+=7) {
/* We rotate the interrupt pins so that the mapping
* changes depending on the slot the carrier card is in.
*/
map[3] = ((map[3] + slot - 2) % 4) + 1;
map+=7;
}
} else {
printf("*** Warning - No PCI node found\n");
}
}
#endif

1
board/cm5200/cm5200.c
View File

@ -397,6 +397,7 @@ int misc_init_r(void)
"operational\n");
/* set the hostname appropriate to the module we're running on */
hostname[0] = 0x00;
compose_hostname(hw_id, hostname);
setenv("hostname", hostname);

1
board/cogent/u-boot.lds
View File

@ -55,6 +55,7 @@ SECTIONS
{
*(.text)
common/environment.o(.text)
*(.fixup)
*(.got1)
}
_etext = .;

4
board/dbau1x00/dbau1x00.c
View File

@ -25,6 +25,7 @@
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
long int initdram(int board_type)
{
@ -77,6 +78,9 @@ int checkboard (void)
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
set_io_port_base(0);
#ifdef CONFIG_IDE_PCMCIA
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */

29
board/dbau1x00/u-boot.lds
View File

@ -43,21 +43,22 @@ SECTIONS
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
_gp = ALIGN(16) + 0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;

5
board/freescale/common/pixis.c
View File

@ -207,13 +207,16 @@ void read_from_px_regs_altbank(int set)
out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
}
#ifndef CFG_PIXIS_VBOOT_MASK
#define CFG_PIXIS_VBOOT_MASK 0x40
#endif
void set_altbank(void)
{
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
tmp ^= 0x40;
tmp ^= CFG_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}

22
board/freescale/common/pq-mds-pib.c
View File

@ -79,19 +79,19 @@ int pib_init(void)
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_MPC832XEMDS)
val = 0;
i2c_write(0x26, 0x7, 1, &val, 1);
val = 0xf7;
i2c_write(0x26, 0x3, 1, &val, 1);
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;
i2c_write(0x26, 0x3, 1, &val8, 1);
val = 0;
i2c_write(0x21, 0x6, 1, &val, 1);
i2c_write(0x21, 0x7, 1, &val, 1);
val8 = 0;
i2c_write(0x21, 0x6, 1, &val8, 1);
i2c_write(0x21, 0x7, 1, &val8, 1);
val = 0xdf;
i2c_write(0x21, 0x2, 1, &val, 1);
val = 0xef;
i2c_write(0x21, 0x3, 1, &val, 1);
val8 = 0xdf;
i2c_write(0x21, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x21, 0x3, 1, &val8, 1);
eieio();

4
board/freescale/m54455evb/config.mk
View File

@ -22,4 +22,6 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

144
board/freescale/m54455evb/u-boot.atm Normal file
View File

@ -0,0 +1,144 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5445x/start.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

141
board/freescale/m54455evb/u-boot.int Normal file
View File

@ -0,0 +1,141 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5445x/start.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

2
board/freescale/mpc8544ds/mpc8544ds.c
View File

@ -227,7 +227,7 @@ pci_init_board(void)
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
in_be32(CFG_PCIE3_MEM_BASE);
in_be32((u32 *)CFG_PCIE3_MEM_BASE);
} else {
printf (" PCIE3: disabled\n");
}

8
board/gth2/gth2.c
View File

@ -26,14 +26,13 @@
#include <asm/au1x00.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <watchdog.h>
#include "ee_access.h"
static int wdi_status = 0;
unsigned long mips_io_port_base = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
@ -147,6 +146,9 @@ int checkboard (void)
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
set_io_port_base(0);
#ifdef CONFIG_IDE_PCMCIA
/* PCMCIA is on a 36 bit physical address.
We need to map it into a 32 bit addresses */
@ -429,7 +431,7 @@ int misc_init_r(void){
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
printf ("*** ethernet addr invalid, using default ***\n");
} else {
setenv ("ethaddr", Rx);
setenv ("ethaddr", (char *)Rx);
}
return (0);
}

4
board/gth2/lowlevel_init.S
View File

@ -413,7 +413,9 @@ noCacheJump:
j clearmem
nop
#if 0
.globl memtest
#endif
memtest:
/* Fill memory with address */
li t0, 0x80000000
@ -434,7 +436,9 @@ mt1: lw t2, 0(t0)
bne t1, zero, mt1
nop
nop
#if 0
.globl clearmem
#endif
clearmem:
/* Clear memory */
li t0, 0x80000000

22
board/gth2/u-boot.lds
View File

@ -43,20 +43,22 @@ SECTIONS
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;

1
board/hymod/u-boot.lds
View File

@ -69,6 +69,7 @@ SECTIONS
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

106
board/ids8247/ids8247.c
View File

@ -25,6 +25,12 @@
#include <ioports.h>
#include <mpc8260.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
@ -38,12 +44,12 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */
/* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
/* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
/* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
/* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
/* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
/* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
#if defined(CONFIG_SOFT_I2C)
/* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
@ -53,14 +59,14 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
#endif
/* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
/* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
/* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
/* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
@ -79,20 +85,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
@ -123,8 +129,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
@ -180,7 +186,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */
/* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
@ -224,7 +230,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
* mapped by the controller. That means, that the initial mapping has
* to be (at least) twice as large as the maximum expected size.
*/
maxsize = (1 + (~orx | 0x7fff)) / 2;
maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
sdmr_ptr = &memctl->memc_psdmr;
orx_ptr = &memctl->memc_or2;
@ -315,4 +321,38 @@ nand_init (void)
printf ("%4lu MB\n", totlen >>20);
}
#endif
#endif /* CFG_CMD_NAND */
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
/*
* update "memory" property in the blob
*/
void ft_blob_update(void *blob, bd_t *bd)
{
int ret, nodeoffset = 0;
ulong memory_data[2] = {0};
memory_data[0] = cpu_to_be32(bd->bi_memstart);
memory_data[1] = cpu_to_be32(bd->bi_memsize);
nodeoffset = fdt_find_node_by_path (blob, "/memory");
if (nodeoffset >= 0) {
ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
sizeof(memory_data));
if (ret < 0)
printf("ft_blob_update): cannot set /memory/reg "
"property err:%s\n", fdt_strerror(ret));
}
else {
/* memory node is required in dts */
printf("ft_blob_update(): cannot find /memory node "
"err:%s\n", fdt_strerror(nodeoffset));
}
}
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup( blob, bd);
ft_blob_update(blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

5
board/incaip/incaip.c
View File

@ -25,7 +25,7 @@
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
#include <asm/io.h>
extern uint incaip_get_cpuclk(void);
@ -85,7 +85,6 @@ long int initdram(int board_type)
int checkboard (void)
{
unsigned long chipid = *INCA_IP_WDT_CHIPID;
int part_num;
@ -107,5 +106,7 @@ int checkboard (void)
printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
set_io_port_base(0);
return 0;
}

29
board/incaip/u-boot.lds
View File

@ -43,21 +43,22 @@ SECTIONS
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
_gp = ALIGN(16) + 0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;

2
board/innokom/innokom.c
View File

@ -72,7 +72,7 @@ int i2c_init_board(void)
int misc_init_r(void)
{
uchar *str;
char *str;
/* determine if the software update key is pressed during startup */
if (GPLR0 & 0x00000800) {

26
board/lwmon5/lwmon5.c
View File

@ -96,6 +96,23 @@ int board_early_init_f(void)
gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
/*
* Reset PHY's:
* The PHY's need a 2nd reset pulse, since the MDIO address is latched
* upon reset, and with the first reset upon powerup, the addresses are
* not latched reliable, since the IRQ line is multiplexed with an
* MDIO address. A 2nd reset at this time will make sure, that the
* correct address is latched.
*/
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
udelay(1000);
gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
udelay(1000);
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
return 0;
}
@ -230,15 +247,6 @@ int misc_init_r(void)
/* Write lime controller memory parameters */
out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
/*
* Reset PHY's
*/
gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
udelay(100);
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
/*
* Init display controller
*/

1
board/m5282evb/m5282evb.c
View File

@ -89,4 +89,5 @@ long int initdram (int board_type)
/* Write to the SDRAM Mode Register */
*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
}

6
board/motionpro/motionpro.c
View File

@ -138,6 +138,12 @@ long int initdram(int board_type)
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* According to AN3221 (MPC5200B SDRAM Initialization and
* Configuration), the SDelay register must be written a value of
* 0x00000004 as the first step of the SDRAM contorller configuration.
*/
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
/* configure SDRAM start/end for detection */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */

1
board/mousse/u-boot.lds
View File

@ -60,6 +60,7 @@ SECTIONS
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)

2
board/mpl/vcma9/flash.c
View File

@ -290,7 +290,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
* Copy memory to flash
*/
volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;

4
board/mpl/vcma9/vcma9.c
View File

@ -288,7 +288,7 @@ int dram_init(void)
int checkboard(void)
{
unsigned char s[50];
char s[50];
int i;
backup_t *b = (backup_t *) s;
@ -337,7 +337,7 @@ int overwrite_console(void)
************************************************************************/
void print_vcma9_info(void)
{
unsigned char s[50];
char s[50];
int i;
if ((i = getenv_r("serial#", s, 32)) < 0) {

2
board/mpl/vcma9/vcma9.h
View File

@ -128,7 +128,7 @@ typedef struct {
} /*__attribute__((__packed__))*/ VCMA9_PLD;
#define VCMA9_PLD_BASE 0x2C000100
static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void)
static inline VCMA9_PLD * VCMA9_GetBase_PLD(void)
{
return (VCMA9_PLD * const)VCMA9_PLD_BASE;
}

2
board/pb1x00/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o
SOBJS = memsetup.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

4
board/pb1x00/memsetup.S → board/pb1x00/lowlevel_init.S
View File

@ -15,8 +15,8 @@
.set noreorder
.set mips32
.globl memsetup
memsetup:
.globl lowlevel_init
lowlevel_init:
/*
* Step 1) Establish CPU endian mode.
* NOTE: A fair amount of code is necessary on the Pb1000 to

6
board/pb1x00/pb1x00.c
View File

@ -25,6 +25,7 @@
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
long int initdram(int board_type)
{
@ -41,7 +42,9 @@ void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
int checkboard (void)
{
#if defined(CONFIG_IDE_PCMCIA) && 0
u16 status;
#endif
/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
u32 proc_id;
@ -69,6 +72,9 @@ int checkboard (void)
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
set_io_port_base(0);
#if defined(CONFIG_IDE_PCMCIA) && 0
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */

22
board/pb1x00/u-boot.lds
View File

@ -43,20 +43,22 @@ SECTIONS
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;

2
board/pleb2/flash.c
View File

@ -196,7 +196,7 @@ void flash_print_info (flash_info_t * info)
int i;
uchar *boottype;
uchar *bootletter;
uchar *fmt;
char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";

2
board/purple/flash.c
View File

@ -299,7 +299,7 @@ void flash_print_info (flash_info_t *info)
int i;
uchar *boottype;
uchar *bootletter;
uchar *fmt;
char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";

3
board/purple/purple.c
View File

@ -26,6 +26,7 @@
#include <asm/inca-ip.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
@ -145,6 +146,8 @@ int checkboard (void)
printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
set_io_port_base(0);
return 0;
}

29
board/purple/u-boot.lds
View File

@ -53,21 +53,22 @@ SECTIONS
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
_gp = ALIGN(16) + 0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;

2
board/pxa255_idp/Makefile
View File

@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := pxa_idp.o
SOBJS := memsetup.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

2
board/pxa255_idp/config.mk
View File

@ -1,3 +1,3 @@
#TEXT_BASE = 0xa1700000
TEXT_BASE = 0xa3000000
TEXT_BASE = 0xa3080000
#TEXT_BASE = 0

10
board/pxa255_idp/memsetup.S → board/pxa255_idp/lowlevel_init.S
View File

@ -3,7 +3,7 @@
*
* NOTE: I haven't clean this up considerably, just enough to get it
* running. See hal_platform_setup.h for the source. See
* board/cradle/memsetup.S for another PXA250 setup that is
* board/cradle/lowlevel_init.S for another PXA250 setup that is
* much cleaner.
*
* See file CREDITS for list of people who contributed to this
@ -41,8 +41,8 @@ DRAM_SIZE: .long CFG_DRAM_SIZE
/*
* Memory setup
*/
.globl memsetup
memsetup:
.globl lowlevel_init
lowlevel_init:
mov r10, lr
@ -395,7 +395,7 @@ initclks:
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
str r8, [r1]
str r8, [r1]
/* Interrupt init: Mask all interrupts */
ldr r0, =ICMR /* enable no sources */
@ -426,7 +426,7 @@ initclks:
bl blink
#endif
endmemsetup:
endlowlevel_init:
mov pc, r10

1
board/pxa255_idp/u-boot.lds
View File

@ -44,6 +44,7 @@ SECTIONS
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;

4
board/rsdproto/rsdproto.c
View File

@ -210,7 +210,7 @@ void read_RS5C372_time (struct tm *timedate)
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
if (i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
timedate->tm_sec = BCD_TO_BIN (buffer[0]);
timedate->tm_min = BCD_TO_BIN (buffer[1]);
timedate->tm_hour = BCD_TO_BIN (buffer[2]);
@ -231,7 +231,7 @@ int read_LM84_temp (int address)
unsigned char buffer[8];
/*int rc;*/
if (i2c_read (address, 0, 1, buffer, 1)) {
if (! i2c_read (address, 0, 1, buffer, 1)) {
return (int) buffer[0];
} else {
/*printf("i2c error %02x\n", rc); */

1
board/rsdproto/u-boot.lds
View File

@ -55,6 +55,7 @@ SECTIONS
{
cpu/mpc8260/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
/*. = env_offset; */
}

2
board/sbc2410x/flash.c
View File

@ -288,7 +288,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
* Copy memory to flash
*/
volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;

2
board/smdk2410/flash.c
View File

@ -290,7 +290,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
* Copy memory to flash
*/
volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;

7
board/tb0229/tb0229.c
View File

@ -13,10 +13,9 @@
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
#include <asm/io.h>
#include <pci.h>
unsigned long mips_io_port_base = 0;
#if defined(CONFIG_PCI)
static struct pci_controller hose;
@ -26,17 +25,17 @@ void pci_init_board (void)
}
#endif
long int initdram(int board_type)
{
return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
}
int checkboard (void)
{
printf("Board: TANBAC TB0229 ");
printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
set_io_port_base(0);
return 0;
}

29
board/tb0229/u-boot.lds
View File

@ -43,21 +43,22 @@ SECTIONS
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
_gp = ALIGN(16) + 0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;

17
board/tqm5200/cmd_stk52xx.c
View File

@ -561,7 +561,7 @@ void led_init(void)
gpt->gpt6.emsr |= 0x00000024;
gpt->gpt7.emsr |= 0x00000024;
#ifndef CONFIG_TQM5200S
/* enable SM501 GPIO control (in both power modes) */
*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
POWER_MODE_GATE_GPIO_PWM_I2C;
@ -574,6 +574,7 @@ void led_init(void)
/* configure SM501 gpio pins 48-51 as output */
*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
#endif /* !CONFIG_TQM5200S */
}
/*
@ -650,7 +651,7 @@ int do_led(char *argv[])
gpt->gpt7.emsr &= ~(1 << 4);
}
break;
#ifndef CONFIG_TQM5200S
case 24:
if (strcmp (argv[3], "on") == 0) {
*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
@ -730,7 +731,7 @@ int do_led(char *argv[])
~(0x1 << 19);
}
break;
#endif /* !CONFIG_TQM5200S */
default:
printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
return 1;
@ -1110,7 +1111,7 @@ int do_rs232(char *argv[])
return error_status;
}
#ifndef CONFIG_FO300
#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
static void sm501_backlight (unsigned int state)
{
if (state == BL_ON) {
@ -1120,7 +1121,7 @@ static void sm501_backlight (unsigned int state)
*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
~((1 << 26) | (1 << 27));
}
#endif
#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
@ -1160,7 +1161,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
else
printf ("Error\n");
return rcode;
#ifndef CONFIG_FO300
#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
} else if (strncmp (argv[1], "backlight", 4) == 0) {
if (strncmp (argv[2], "on", 2) == 0) {
sm501_backlight (BL_ON);
@ -1170,7 +1171,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
sm501_backlight (BL_OFF);
return 0;
}
#endif
#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
}
break;
@ -1228,8 +1229,10 @@ U_BOOT_CMD(
" - loopback plug for X83 required\n"
"fkt rs232 number\n"
" - loopback plug(s) for X2 required\n"
#ifndef CONFIG_TQM5200S
"fkt backlight on/off\n"
" - switch backlight on or off\n"
#endif /* !CONFIG_TQM5200S */
);
#elif defined(CONFIG_FO300)
U_BOOT_CMD(

14
board/tqm5200/tqm5200.c
View File

@ -441,15 +441,23 @@ ulong post_word_load (void)
}
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
#ifdef CONFIG_PS2MULT
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
extern int usb_cpu_init(void);
#ifdef CONFIG_PS2MULT
ps2mult_early_init();
#endif /* CONFIG_PS2MULT */
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
/* Low level USB init, required for proper kernel operation */
usb_cpu_init();
#endif
return (0);
}
#endif
#endif /* CONFIG_PS2MULT */
#ifdef CONFIG_FO300
int silent_boot (void)
@ -543,6 +551,7 @@ int last_stage_init (void)
__asm__ volatile ("sync");
}
#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
/*
* Check for Grafic Controller
*/
@ -584,6 +593,7 @@ int last_stage_init (void)
disable_ctrlc(1);
}
#endif
#endif /* !CONFIG_TQM5200S */
return 0;
}

16
board/tqm8xx/tqm8xx.c
View File

@ -354,6 +354,8 @@ long int initdram (int board_type)
udelay (10000);
#ifdef CONFIG_CAN_DRIVER
/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
/* Initialize OR3 / BR3 */
memctl->memc_or3 = CFG_OR3_CAN;
memctl->memc_br3 = CFG_BR3_CAN;
@ -362,7 +364,7 @@ long int initdram (int board_type)
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;
memctl->memc_mdr = 0xFFFFCC04;
memctl->memc_mcr = 0x0100 | UPMB;
memctl->memc_mdr = 0x0FFFD004;
@ -374,23 +376,23 @@ long int initdram (int board_type)
memctl->memc_mdr = 0x3FFFC004;
memctl->memc_mcr = 0x0103 | UPMB;
memctl->memc_mdr = 0xFFFFDC05;
memctl->memc_mdr = 0xFFFFDC07;
memctl->memc_mcr = 0x0104 | UPMB;
/* Initialize UPMB for CAN: single write */
memctl->memc_mdr = 0xFFFCC004;
memctl->memc_mdr = 0xFFFCCC04;
memctl->memc_mcr = 0x0118 | UPMB;
memctl->memc_mdr = 0xCFFCD004;
memctl->memc_mdr = 0xCFFCDC04;
memctl->memc_mcr = 0x0119 | UPMB;
memctl->memc_mdr = 0x0FFCC000;
memctl->memc_mdr = 0x3FFCC000;
memctl->memc_mcr = 0x011A | UPMB;
memctl->memc_mdr = 0x7FFCC004;
memctl->memc_mdr = 0xFFFCC004;
memctl->memc_mcr = 0x011B | UPMB;
memctl->memc_mdr = 0xFFFDCC05;
memctl->memc_mdr = 0xFFFDC405;
memctl->memc_mcr = 0x011C | UPMB;
#endif /* CONFIG_CAN_DRIVER */

5
board/wepep250/flash.c
View File

@ -44,6 +44,7 @@
#if ( WEP_FLASH_BUS_WIDTH == 1 )
# define FLASH_BUS vu_char
# define FLASH_BUS_RET u_char
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# else
@ -53,6 +54,7 @@
#elif ( WEP_FLASH_BUS_WIDTH == 2 )
# define FLASH_BUS vu_short
# define FLASH_BUS_RET u_short
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# elif ( WEP_FLASH_INTERLEAVE == 2 )
@ -64,6 +66,7 @@
#elif ( WEP_FLASH_BUS_WIDTH == 4 )
# define FLASH_BUS vu_long
# define FLASH_BUS_RET u_long
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# elif ( WEP_FLASH_INTERLEAVE == 2 )
@ -81,7 +84,7 @@
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
static FLASH_BUS flash_status_reg (void)
static FLASH_BUS_RET flash_status_reg (void)
{
FLASH_BUS *addr = (FLASH_BUS *) 0;

4
board/xsengine/flash.c
View File

@ -46,11 +46,11 @@ unsigned long flash_init (void)
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]);
flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
case 1:
flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]);
flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
break;
default:

122
common/Makefile
View File

@ -27,31 +27,105 @@ LIB = $(obj)libcommon.a
AOBJS =
COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \
cmd_cache.o cmd_console.o \
cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \
cmd_eeprom.o cmd_elf.o cmd_ext2.o \
cmd_fat.o cmd_fdc.o cmd_fdt.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
cmd_load.o cmd_log.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_net.o cmd_nvedit.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \
cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
cmd_universe.o cmd_usb.o cmd_vfd.o \
command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
environment.o env_common.o \
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
env_nvram.o env_nowhere.o \
exports.o \
fdt_support.o flash.o fpga.o ft_build.o \
hush.o kgdb.o lcd.o lists.o lynxkdi.o \
memsize.o miiphybb.o miiphyutil.o \
s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
usb.o usb_kbd.o usb_storage.o \
virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o cmd_mfsl.o
COBJS-y += main.o
COBJS-y += ACEX1K.o
COBJS-y += altera.o
COBJS-y += bedbug.o
COBJS-y += circbuf.o
COBJS-y += cmd_autoscript.o
COBJS-y += cmd_bdinfo.o
COBJS-y += cmd_bedbug.o
COBJS-y += cmd_bmp.o
COBJS-y += cmd_boot.o
COBJS-y += cmd_bootm.o
COBJS-y += cmd_cache.o
COBJS-y += cmd_console.o
COBJS-y += cmd_date.o
COBJS-y += cmd_dcr.o
COBJS-y += cmd_diag.o
COBJS-y += cmd_display.o
COBJS-y += cmd_doc.o
COBJS-y += cmd_dtt.o
COBJS-y += cmd_eeprom.o
COBJS-y += cmd_elf.o
COBJS-y += cmd_ext2.o
COBJS-y += cmd_fat.o
COBJS-y += cmd_fdc.o
COBJS-y += cmd_fdt.o
COBJS-y += cmd_fdos.o
COBJS-y += cmd_flash.o
COBJS-y += cmd_fpga.o
COBJS-y += cmd_i2c.o
COBJS-y += cmd_ide.o
COBJS-y += cmd_immap.o
COBJS-y += cmd_itest.o
COBJS-y += cmd_jffs2.o
COBJS-y += cmd_load.o
COBJS-y += cmd_log.o
COBJS-y += cmd_mem.o
COBJS-y += cmd_mii.o
COBJS-y += cmd_misc.o
COBJS-y += cmd_mmc.o
COBJS-y += cmd_nand.o
COBJS-y += cmd_net.o
COBJS-y += cmd_nvedit.o
COBJS-y += cmd_onenand.o
COBJS-y += cmd_pci.o
COBJS-y += cmd_pcmcia.o
COBJS-y += cmd_portio.o
COBJS-y += cmd_reginfo.o
COBJS-y += cmd_reiser.o
COBJS-y += cmd_sata.o
COBJS-y += cmd_scsi.o
COBJS-y += cmd_spi.o
COBJS-y += cmd_universe.o
COBJS-y += cmd_usb.o
COBJS-y += cmd_vfd.o
COBJS-y += command.o
COBJS-y += console.o
COBJS-y += cyclon2.o
COBJS-y += devices.o
COBJS-y += dlmalloc.o
COBJS-y += docecc.o
COBJS-y += environment.o
COBJS-y += env_common.o
COBJS-y += env_nand.o
COBJS-y += env_dataflash.o
COBJS-y += env_flash.o
COBJS-y += env_eeprom.o
COBJS-y += env_onenand.o
COBJS-y += env_nvram.o
COBJS-y += env_nowhere.o
COBJS-y += exports.o
COBJS-y += fdt_support.o
COBJS-y += flash.o
COBJS-y += fpga.o
COBJS-y += ft_build.o
COBJS-y += hush.o
COBJS-y += kgdb.o
COBJS-y += lcd.o
COBJS-y += lists.o
COBJS-y += lynxkdi.o
COBJS-y += memsize.o
COBJS-y += miiphybb.o
COBJS-y += miiphyutil.o
COBJS-y += s_record.o
COBJS-y += serial.o
COBJS-y += soft_i2c.o
COBJS-y += soft_spi.o
COBJS-y += spartan2.o
COBJS-y += spartan3.o
COBJS-y += usb.o
COBJS-y += usb_kbd.o
COBJS-y += usb_storage.o
COBJS-y += virtex2.o
COBJS-y += xilinx.o
COBJS-y += crc16.o
COBJS-y += xyzModem.o
COBJS-y += cmd_mac.o
COBJS-y += cmd_mfsl.o
COBJS := $(COBJS-y)
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))

2
common/cmd_bootm.c
View File

@ -468,7 +468,7 @@ U_BOOT_CMD(
"\t'arg' can be the address of an initrd image\n"
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
"\tWhen booting a Linux kernel which requires a flat device-tree\n"
"\ta third argument is required which is the address of the of the\n"
"\ta third argument is required which is the address of the\n"
"\tdevice-tree blob. To boot that kernel without an initrd image,\n"
"\tuse a '-' for the second argument. If you do not pass a third\n"
"\ta bd_info struct will be passed instead\n"

2
common/cmd_dtt.c
View File

@ -57,7 +57,7 @@ int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
dtt, 1, 1, do_dtt,
"dtt - Digital Thermometer and Themostat\n",
"dtt - Digital Thermometer and Thermostat\n",
" - Read temperature from digital thermometer and thermostat.\n"
);

2
common/cmd_fpga.c
View File

@ -60,6 +60,7 @@ static int fpga_get_op (char *opstr);
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
#if (CONFIG_FPGA & CFG_FPGA_XILINX)
unsigned int length;
unsigned char* swapdata;
unsigned int swapsize;
@ -72,7 +73,6 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
dataptr = (unsigned char *)fpgadata;
#if CFG_FPGA_XILINX
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;

16
common/cmd_ide.c
View File

@ -54,10 +54,6 @@
#ifndef __PPC__
#include <asm/io.h>
#ifdef __MIPS__
/* Macros depend on this variable */
unsigned long mips_io_port_base = 0;
#endif
#endif
#ifdef CONFIG_IDE_8xx_DIRECT
@ -1136,9 +1132,9 @@ static void ide_ident (block_dev_desc_t *dev_desc)
input_swap_data (device, iobuf, ATA_SECTORWORDS);
ident_cpy (dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision));
ident_cpy (dev_desc->vendor, iop->model, sizeof(dev_desc->vendor));
ident_cpy (dev_desc->product, iop->serial_no, sizeof(dev_desc->product));
ident_cpy ((unsigned char*)dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision));
ident_cpy ((unsigned char*)dev_desc->vendor, iop->model, sizeof(dev_desc->vendor));
ident_cpy ((unsigned char*)dev_desc->product, iop->serial_no, sizeof(dev_desc->product));
#ifdef __LITTLE_ENDIAN
/*
* firmware revision and model number have Big Endian Byte
@ -1953,9 +1949,9 @@ static void atapi_inquiry(block_dev_desc_t * dev_desc)
return;
/* copy device ident strings */
ident_cpy(dev_desc->vendor,&iobuf[8],8);
ident_cpy(dev_desc->product,&iobuf[16],16);
ident_cpy(dev_desc->revision,&iobuf[32],5);
ident_cpy((unsigned char*)dev_desc->vendor,&iobuf[8],8);
ident_cpy((unsigned char*)dev_desc->product,&iobuf[16],16);
ident_cpy((unsigned char*)dev_desc->revision,&iobuf[32],5);
dev_desc->lun=0;
dev_desc->lba=0;

16
common/cmd_mfsl.c
View File

@ -355,19 +355,18 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
unsigned int reg = 0;
unsigned int val = 0;
reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
if (argc < 1) {
if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
switch (reg) {
case 0x1:
if (argc > 2) {
MTS (val, rmsr);
NOP;
MFS (val, rmsr);
} else {
MFS (val, rmsr);
}
@ -382,6 +381,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
puts ("ESR");
break;
default:
puts ("Unsupported register\n");
return 1;
}
printf (": 0x%08lx\n", val);
@ -408,10 +408,10 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
" 3 - blocking control write\n");
U_BOOT_CMD (rspr, 3, 1, do_rspr,
"rmsr - read/write special purpose register\n",
"rspr - read/write special purpose register\n",
"- reg_num [write value] read/write special purpose register\n"
" 0 - MSR - Machine status register\n"
" 1 - EAR - Exception address register\n"
" 2 - ESR - Exception status register\n");
" 1 - MSR - Machine status register\n"
" 3 - EAR - Exception address register\n"
" 5 - ESR - Exception status register\n");
#endif

8
common/cmd_mii.c
View File

@ -112,9 +112,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbaseT, %s\n",
"%3dbase%s, %s\n",
j, oui, model, rev,
miiphy_speed (devname, j),
miiphy_is_1000base_x (devname, j)
? "X" : "T",
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
}
@ -496,9 +498,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbaseT, %s\n",
"%3dbase%s, %s\n",
j, oui, model, rev,
miiphy_speed (devname, j),
miiphy_is_1000base_x (devname, j)
? "X" : "T",
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
}

9
common/cmd_nvedit.c
View File

@ -57,8 +57,9 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CFG_ENV_IS_IN_FLASH) && \
!defined(CFG_ENV_IS_IN_DATAFLASH) && \
!defined(CFG_ENV_IS_IN_NAND) && \
!defined(CFG_ENV_IS_IN_ONENAND) && \
!defined(CFG_ENV_IS_NOWHERE)
# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE}
# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE}
#endif
#define XMK_STR(x) #x
@ -553,7 +554,8 @@ int getenv_r (char *name, char *buf, unsigned len)
#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
extern char * env_name_spec;
@ -608,7 +610,8 @@ U_BOOT_CMD(
#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
U_BOOT_CMD(
saveenv, 1, 0, do_saveenv,
"saveenv - save environment variables to persistent storage\n",

155
common/cmd_onenand.c Normal file
View File

@ -0,0 +1,155 @@
/*
* U-Boot command for OneNAND support
*
* Copyright (C) 2005-2007 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <command.h>
#ifdef CONFIG_CMD_ONENAND
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <asm/io.h>
extern struct mtd_info onenand_mtd;
extern struct onenand_chip onenand_chip;
int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int ret = 0;
switch (argc) {
case 0:
case 1:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
case 2:
if (strncmp(argv[1], "open", 4) == 0) {
onenand_init();
return 0;
}
onenand_print_device_info(onenand_chip.device_id, 1);
return 0;
default:
/* At least 4 args */
if (strncmp(argv[1], "erase", 5) == 0) {
struct erase_info instr;
ulong start, end;
ulong block;
start = simple_strtoul(argv[2], NULL, 10);
end = simple_strtoul(argv[3], NULL, 10);
start -= (unsigned long)onenand_chip.base;
end -= (unsigned long)onenand_chip.base;
if (!end || end < 0)
end = start;
printf("Erase block from %d to %d\n", start, end);
for (block = start; block <= end; block++) {
instr.addr = block << onenand_chip.erase_shift;
instr.len = 1 << onenand_chip.erase_shift;
ret = onenand_erase(&onenand_mtd, &instr);
if (ret) {
printf("erase failed %d\n", block);
break;
}
}
return 0;
}
if (strncmp(argv[1], "read", 4) == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong ofs = simple_strtoul(argv[3], NULL, 16);
size_t len = simple_strtoul(argv[4], NULL, 16);
size_t retlen = 0;
int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1;
ofs -= (unsigned long)onenand_chip.base;
if (oob)
onenand_read_oob(&onenand_mtd, ofs, len,
&retlen, (u_char *) addr);
else
onenand_read(&onenand_mtd, ofs, len, &retlen,
(u_char *) addr);
printf("Done\n");
return 0;
}
if (strncmp(argv[1], "write", 5) == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong ofs = simple_strtoul(argv[3], NULL, 16);
size_t len = simple_strtoul(argv[4], NULL, 16);
size_t retlen = 0;
ofs -= (unsigned long)onenand_chip.base;
onenand_write(&onenand_mtd, ofs, len, &retlen,
(u_char *) addr);
printf("Done\n");
return 0;
}
if (strncmp(argv[1], "block", 5) == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong block = simple_strtoul(argv[3], NULL, 10);
ulong page = simple_strtoul(argv[4], NULL, 10);
size_t len = simple_strtol(argv[5], NULL, 10);
size_t retlen = 0;
ulong ofs;
int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1;
ofs = block << onenand_chip.erase_shift;
if (page)
ofs += page << onenand_chip.page_shift;
if (!len) {
if (oob)
len = 64;
else
len = 512;
}
if (oob)
onenand_read_oob(&onenand_mtd, ofs, len,
&retlen, (u_char *) addr);
else
onenand_read(&onenand_mtd, ofs, len, &retlen,
(u_char *) addr);
return 0;
}
break;
}
return 0;
}
U_BOOT_CMD(
onenand, 6, 1, do_onenand,
"onenand - OneNAND sub-system\n",
"info - show available OneNAND devices\n"
"onenand read[.oob] addr ofs len - read data at ofs with len to addr\n"
"onenand write addr ofs len - write data at ofs with len from addr\n"
"onenand erase saddr eaddr - erase block start addr to end addr\n"
"onenand block[.oob] addr block [page] [len] - "
"read data with (block [, page]) to addr"
);
#endif /* CONFIG_CMD_ONENAND */

9
common/cmd_scsi.c
View File

@ -129,9 +129,12 @@ void scsi_scan(int mode)
if((modi&0x80)==0x80) /* drive is removable */
scsi_dev_desc[scsi_max_devs].removable=TRUE;
/* get info for this device */
scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].vendor[0],&tempbuff[8],8);
scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].product[0],&tempbuff[16],16);
scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].revision[0],&tempbuff[32],4);
scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
&tempbuff[8], 8);
scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0],
&tempbuff[16], 16);
scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
&tempbuff[32], 4);
scsi_dev_desc[scsi_max_devs].target=pccb->target;
scsi_dev_desc[scsi_max_devs].lun=pccb->lun;

134
common/env_onenand.c Normal file
View File

@ -0,0 +1,134 @@
/*
* (C) Copyright 2005-2007 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CFG_ENV_IS_IN_ONENAND) /* Environment is in OneNAND */
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
extern struct mtd_info onenand_mtd;
extern struct onenand_chip onenand_chip;
/* References to names in env_common.c */
extern uchar default_environment[];
#define ONENAND_ENV_SIZE(mtd) (mtd.oobblock - ENV_HEADER_SIZE)
char *env_name_spec = "OneNAND";
#ifdef ENV_IS_EMBEDDED
extern uchar environment[];
env_t *env_ptr = (env_t *) (&environment[0]);
#else /* ! ENV_IS_EMBEDDED */
static unsigned char onenand_env[MAX_ONENAND_PAGESIZE];
env_t *env_ptr = (env_t *) onenand_env;
#endif /* ENV_IS_EMBEDDED */
uchar env_get_char_spec(int index)
{
DECLARE_GLOBAL_DATA_PTR;
return (*((uchar *) (gd->env_addr + index)));
}
void env_relocate_spec(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned long env_addr;
int use_default = 0;
int retlen;
env_addr = CFG_ENV_ADDR;
env_addr -= (unsigned long)onenand_chip.base;
/* Check OneNAND exist */
if (onenand_mtd.oobblock)
/* Ignore read fail */
onenand_read(&onenand_mtd, env_addr, onenand_mtd.oobblock,
&retlen, (u_char *) env_ptr);
else
onenand_mtd.oobblock = MAX_ONENAND_PAGESIZE;
if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) !=
env_ptr->crc)
use_default = 1;
if (use_default) {
memcpy(env_ptr->data, default_environment,
ONENAND_ENV_SIZE(onenand_mtd));
env_ptr->crc =
crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
}
gd->env_addr = (ulong) & env_ptr->data;
gd->env_valid = 1;
}
int saveenv(void)
{
unsigned long env_addr = CFG_ENV_ADDR;
struct erase_info instr;
int retlen;
instr.len = CFG_ENV_SIZE;
instr.addr = env_addr;
instr.addr -= (unsigned long)onenand_chip.base;
if (onenand_erase(&onenand_mtd, &instr)) {
printf("OneNAND: erase failed at 0x%08x\n", env_addr);
return 1;
}
/* update crc */
env_ptr->crc =
crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE);
env_addr -= (unsigned long)onenand_chip.base;
if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen,
(u_char *) env_ptr)) {
printf("OneNAND: write failed at 0x%08x\n", instr.addr);
return 2;
}
return 0;
}
int env_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
/* use default */
gd->env_addr = (ulong) & default_environment[0];
gd->env_valid = 1;
return 0;
}
#endif /* CFG_ENV_IS_IN_ONENAND */

282
common/miiphyutil.c
View File

@ -49,10 +49,10 @@
struct mii_dev {
struct list_head link;
char *name;
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
int (*read) (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int (*write) (char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
};
static struct list_head mii_devs;
@ -62,21 +62,21 @@ static struct mii_dev *current_mii;
*
* Initialize global data. Need to be called before any other miiphy routine.
*/
void miiphy_init()
void miiphy_init ()
{
INIT_LIST_HEAD(&mii_devs);
current_mii = NULL;
INIT_LIST_HEAD (&mii_devs);
current_mii = NULL;
}
/*****************************************************************************
*
* Register read and write MII access routines for the device <name>.
*/
void miiphy_register(char *name,
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value))
void miiphy_register (char *name,
int (*read) (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (*write) (char *devname, unsigned char addr,
unsigned char reg, unsigned short value))
{
struct list_head *entry;
struct mii_dev *new_dev;
@ -84,63 +84,64 @@ void miiphy_register(char *name,
unsigned int name_len;
/* check if we have unique name */
list_for_each(entry, &mii_devs) {
miidev = list_entry(entry, struct mii_dev, link);
if (strcmp(miidev->name, name) == 0) {
printf("miiphy_register: non unique device name '%s'\n",
name);
list_for_each (entry, &mii_devs) {
miidev = list_entry (entry, struct mii_dev, link);
if (strcmp (miidev->name, name) == 0) {
printf ("miiphy_register: non unique device name "
"'%s'\n", name);
return;
}
}
/* allocate memory */
name_len = strlen(name);
new_dev = (struct mii_dev *)malloc(sizeof(struct mii_dev) + name_len + 1);
name_len = strlen (name);
new_dev =
(struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);
if(new_dev == NULL) {
printf("miiphy_register: cannot allocate memory for '%s'\n",
name);
if (new_dev == NULL) {
printf ("miiphy_register: cannot allocate memory for '%s'\n",
name);
return;
}
memset(new_dev, 0, sizeof(struct mii_dev) + name_len);
memset (new_dev, 0, sizeof (struct mii_dev) + name_len);
/* initalize mii_dev struct fields */
INIT_LIST_HEAD(&new_dev->link);
INIT_LIST_HEAD (&new_dev->link);
new_dev->read = read;
new_dev->write = write;
new_dev->name = (char *)(new_dev + 1);
strncpy(new_dev->name, name, name_len);
strncpy (new_dev->name, name, name_len);
new_dev->name[name_len] = '\0';
debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
new_dev->name, new_dev->read, new_dev->write);
debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
new_dev->name, new_dev->read, new_dev->write);
/* add it to the list */
list_add_tail(&new_dev->link, &mii_devs);
list_add_tail (&new_dev->link, &mii_devs);
if (!current_mii)
current_mii = new_dev;
}
int miiphy_set_current_dev(char *devname)
int miiphy_set_current_dev (char *devname)
{
struct list_head *entry;
struct mii_dev *dev;
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
list_for_each (entry, &mii_devs) {
dev = list_entry (entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
if (strcmp (devname, dev->name) == 0) {
current_mii = dev;
return 0;
}
}
printf("No such device: %s\n", devname);
printf ("No such device: %s\n", devname);
return 1;
}
char *miiphy_get_current_dev()
char *miiphy_get_current_dev ()
{
if (current_mii)
return current_mii->name;
@ -156,8 +157,8 @@ char *miiphy_get_current_dev()
* Returns:
* 0 on success
*/
int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
struct list_head *entry;
struct mii_dev *dev;
@ -165,22 +166,22 @@ int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
int read_ret = 0;
if (!devname) {
printf("NULL device name!\n");
printf ("NULL device name!\n");
return 1;
}
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
list_for_each (entry, &mii_devs) {
dev = list_entry (entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
if (strcmp (devname, dev->name) == 0) {
found_dev = 1;
read_ret = dev->read(devname, addr, reg, value);
read_ret = dev->read (devname, addr, reg, value);
break;
}
}
if (found_dev == 0)
printf("No such device: %s\n", devname);
printf ("No such device: %s\n", devname);
return ((found_dev) ? read_ret : 1);
}
@ -193,8 +194,8 @@ int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
* Returns:
* 0 on success
*/
int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
struct list_head *entry;
struct mii_dev *dev;
@ -202,22 +203,22 @@ int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
int write_ret = 0;
if (!devname) {
printf("NULL device name!\n");
printf ("NULL device name!\n");
return 1;
}
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
list_for_each (entry, &mii_devs) {
dev = list_entry (entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
if (strcmp (devname, dev->name) == 0) {
found_dev = 1;
write_ret = dev->write(devname, addr, reg, value);
write_ret = dev->write (devname, addr, reg, value);
break;
}
}
if (found_dev == 0)
printf("No such device: %s\n", devname);
printf ("No such device: %s\n", devname);
return ((found_dev) ? write_ret : 1);
}
@ -226,23 +227,22 @@ int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
*
* Print out list of registered MII capable devices.
*/
void miiphy_listdev(void)
void miiphy_listdev (void)
{
struct list_head *entry;
struct mii_dev *dev;
puts("MII devices: ");
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
printf("'%s' ", dev->name);
puts ("MII devices: ");
list_for_each (entry, &mii_devs) {
dev = list_entry (entry, struct mii_dev, link);
printf ("'%s' ", dev->name);
}
puts("\n");
puts ("\n");
if (current_mii)
printf("Current device: '%s'\n", current_mii->name);
printf ("Current device: '%s'\n", current_mii->name);
}
/*****************************************************************************
*
* Read the OUI, manufacture's model number, and revision number.
@ -254,9 +254,7 @@ void miiphy_listdev(void)
* Returns:
* 0 on success
*/
int miiphy_info (char *devname,
unsigned char addr,
unsigned int *oui,
int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev)
{
unsigned int reg = 0;
@ -288,13 +286,12 @@ int miiphy_info (char *devname,
#ifdef DEBUG
printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
#endif
*oui = ( reg >> 10);
*model = (unsigned char) ((reg >> 4) & 0x0000003F);
*rev = (unsigned char) ( reg & 0x0000000F);
*oui = (reg >> 10);
*model = (unsigned char)((reg >> 4) & 0x0000003F);
*rev = (unsigned char)(reg & 0x0000000F);
return (0);
}
/*****************************************************************************
*
* Reset the PHY.
@ -345,104 +342,138 @@ int miiphy_reset (char *devname, unsigned char addr)
return (0);
}
/*****************************************************************************
*
* Determine the ethernet speed (10/100).
* Determine the ethernet speed (10/100/1000). Return 10 on error.
*/
int miiphy_speed (char *devname, unsigned char addr)
{
unsigned short reg;
u16 bmcr, anlpar;
#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
printf ("PHY 1000BT Status read failed\n");
} else {
if (reg != 0xFFFF) {
if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) {
return (_1000BASET);
}
}
u16 btsr;
/*
* Check for 1000BASE-X. If it is supported, then assume that the speed
* is 1000.
*/
if (miiphy_is_1000base_x (devname, addr)) {
return _1000BASET;
}
/*
* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
*/
/* Check for 1000BASE-T. */
if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
printf ("PHY 1000BT status");
goto miiphy_read_failed;
}
if (btsr != 0xFFFF &&
(btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) {
return _1000BASET;
}
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
puts ("PHY speed read failed, assuming 10bT\n");
return (_10BASET);
if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
printf ("PHY speed");
goto miiphy_read_failed;
}
/* Check if auto-negotiation is on. */
if ((reg & PHY_BMCR_AUTON) != 0) {
if (bmcr & PHY_BMCR_AUTON) {
/* Get auto-negotiation results. */
if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
puts ("PHY AN speed read failed, assuming 10bT\n");
return (_10BASET);
}
if ((reg & PHY_ANLPAR_100) != 0) {
return (_100BASET);
} else {
return (_10BASET);
if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
printf ("PHY AN speed");
goto miiphy_read_failed;
}
return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET;
}
/* Get speed from basic control settings. */
else if (reg & PHY_BMCR_100MB) {
return (_100BASET);
} else {
return (_10BASET);
}
return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET;
miiphy_read_failed:
printf (" read failed, assuming 10BASE-T\n");
return _10BASET;
}
/*****************************************************************************
*
* Determine full/half duplex.
* Determine full/half duplex. Return half on error.
*/
int miiphy_duplex (char *devname, unsigned char addr)
{
unsigned short reg;
u16 bmcr, anlpar;
#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
printf ("PHY 1000BT Status read failed\n");
} else {
if ( (reg != 0xFFFF) &&
(reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) {
if ((reg & PHY_1000BTSR_1000FD) !=0) {
return (FULL);
} else {
return (HALF);
}
u16 btsr;
/* Check for 1000BASE-X. */
if (miiphy_is_1000base_x (devname, addr)) {
/* 1000BASE-X */
if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
printf ("1000BASE-X PHY AN duplex");
goto miiphy_read_failed;
}
}
/*
* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
*/
/* Check for 1000BASE-T. */
if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
printf ("PHY 1000BT status");
goto miiphy_read_failed;
}
if (btsr != 0xFFFF) {
if (btsr & PHY_1000BTSR_1000FD) {
return FULL;
} else if (btsr & PHY_1000BTSR_1000HD) {
return HALF;
}
}
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
puts ("PHY duplex read failed, assuming half duplex\n");
return (HALF);
if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
puts ("PHY duplex");
goto miiphy_read_failed;
}
/* Check if auto-negotiation is on. */
if ((reg & PHY_BMCR_AUTON) != 0) {
if (bmcr & PHY_BMCR_AUTON) {
/* Get auto-negotiation results. */
if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
puts ("PHY AN duplex read failed, assuming half duplex\n");
return (HALF);
}
if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
return (FULL);
} else {
return (HALF);
if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
puts ("PHY AN duplex");
goto miiphy_read_failed;
}
return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ?
FULL : HALF;
}
/* Get speed from basic control settings. */
else if (reg & PHY_BMCR_DPLX) {
return (FULL);
} else {
return (HALF);
}
return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF;
miiphy_read_failed:
printf (" read failed, assuming half duplex\n");
return HALF;
}
/*****************************************************************************
*
* Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
* 1000BASE-T, or on error.
*/
int miiphy_is_1000base_x (char *devname, unsigned char addr)
{
#if defined(CONFIG_PHY_GIGE)
u16 exsr;
if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) {
printf ("PHY extended status read failed, assuming no "
"1000BASE-X\n");
return 0;
}
return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH));
#else
return 0;
#endif
}
#ifdef CFG_FAULT_ECHO_LINK_DOWN
@ -455,7 +486,7 @@ int miiphy_link (char *devname, unsigned char addr)
unsigned short reg;
/* dummy read; needed to latch some phys */
(void)miiphy_read(devname, addr, PHY_BMSR, &reg);
(void)miiphy_read (devname, addr, PHY_BMSR, &reg);
if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
puts ("PHY_BMSR read failed, assuming no link\n");
return (0);
@ -469,5 +500,4 @@ int miiphy_link (char *devname, unsigned char addr)
}
}
#endif
#endif /* CONFIG_MII */

2
common/spartan2.c
View File

@ -516,7 +516,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val < 0), TRUE, cookie);
(*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);

2
common/spartan3.c
View File

@ -521,7 +521,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val < 0), TRUE, cookie);
(*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);

2
common/usb_kbd.c
View File

@ -257,7 +257,7 @@ static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int p
repeat_delay=REPEAT_DELAY;
}
keycode=0;
if((scancode>3) && (scancode<0x1d)) { /* alpha numeric values */
if((scancode>3) && (scancode<=0x1d)) { /* alpha numeric values */
keycode=scancode-4 + 0x61;
if(caps_lock)
keycode&=~CAPITAL_MASK; /* switch to capital Letters */

2
common/usb_storage.c
View File

@ -1195,7 +1195,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
dev_desc->product[16] = 0;
dev_desc->revision[4] = 0;
#ifdef CONFIG_USB_BIN_FIXUP
usb_bin_fixup(dev->descriptor, dev_desc->vendor, dev_desc->product);
usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product);
#endif /* CONFIG_USB_BIN_FIXUP */
USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]);
if(usb_test_unit_ready(pccb,ss)) {

4
config.mk
View File

@ -69,10 +69,6 @@ PLATFORM_CPPFLAGS+= -D__ARM__
endif
endif
ifeq ($(ARCH),blackfin)
PLATFORM_CPPFLAGS+= -D__BLACKFIN__
endif
ifdef ARCH
sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules
endif

2
cpu/arm720t/serial.c
View File

@ -125,6 +125,8 @@ serial_puts (const char *s)
#elif defined(CONFIG_LPC2292)
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/hardware.h>
void serial_setbrg (void)

8
cpu/arm920t/at91rm9200/usb.c
View File

@ -28,7 +28,7 @@
#include <asm/arch/hardware.h>
int usb_cpu_init()
int usb_cpu_init(void)
{
/* Enable USB host clock. */
*AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
@ -36,7 +36,7 @@ int usb_cpu_init()
return 0;
}
int usb_cpu_stop()
int usb_cpu_stop(void)
{
/* Initialization failed */
*AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */
@ -44,9 +44,9 @@ int usb_cpu_stop()
return 0;
}
int usb_cpu_init_fail()
int usb_cpu_init_fail(void)
{
usb_cpu_stop();
return usb_cpu_stop();
}
# endif /* CONFIG_AT91RM9200 */

2
cpu/arm920t/s3c24x0/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = i2c.o interrupts.o serial.o speed.o \
usb.o
usb.o usb_ohci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

14
cpu/arm920t/s3c24x0/usb_ohci.c
View File

@ -498,7 +498,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
if (ohci->ed_controltail == NULL) {
writel (ed, &ohci->regs->ed_controlhead);
} else {
ohci->ed_controltail->hwNextED = m32_swap (ed);
ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed);
}
ed->ed_prev = ohci->ed_controltail;
if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
@ -514,7 +514,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
if (ohci->ed_bulktail == NULL) {
writel (ed, &ohci->regs->ed_bulkhead);
} else {
ohci->ed_bulktail->hwNextED = m32_swap (ed);
ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed);
}
ed->ed_prev = ohci->ed_bulktail;
if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
@ -606,7 +606,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
td = td_alloc (usb_dev);
ed->hwTailP = m32_swap (td);
ed->hwTailP = (__u32)m32_swap (td);
ed->hwHeadP = ed->hwTailP;
ed->state = ED_UNLINK;
ed->type = usb_pipetype (pipe);
@ -663,13 +663,13 @@ static void td_fill (ohci_t *ohci, unsigned int info,
if (!len)
data = 0;
td->hwINFO = m32_swap (info);
td->hwCBP = m32_swap (data);
td->hwINFO = (__u32)m32_swap (info);
td->hwCBP = (__u32)m32_swap (data);
if (data)
td->hwBE = m32_swap (data + len - 1);
td->hwBE = (__u32)m32_swap (data + len - 1);
else
td->hwBE = 0;
td->hwNextTD = m32_swap (td_pt);
td->hwNextTD = (__u32)m32_swap (td_pt);
/* append to queue */
td->ed->hwTailP = td->hwNextTD;

128
cpu/arm920t/start.S
View File

@ -27,9 +27,7 @@
#include <config.h>
#include <version.h>
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
#include <led.h>
#endif
#include <status_led.h>
/*
*************************************************************************
@ -41,7 +39,7 @@
.globl _start
_start: b reset
_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@ -64,7 +62,7 @@ _fiq: .word fiq
/*
*************************************************************************
*
* Startup Code (reset vector)
* Startup Code (called from the ARM reset exception vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
@ -106,10 +104,10 @@ FIQ_STACK_START:
/*
* the actual reset code
* the actual start code
*/
reset:
start_code:
/*
* set the cpu to SVC32 mode
*/
@ -118,58 +116,12 @@ reset:
orr r0,r0,#0xd3
msr cpsr,r0
#if CONFIG_AT91RM9200
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
bl LED_init
bl coloured_LED_init
bl red_LED_on
#endif
#ifdef CONFIG_BOOTBINFUNC
/* code based on entry.S from ATMEL */
#define AT91C_BASE_CKGR 0xFFFFFC20
#define CKGR_MOR 0
/* Get the CKGR Base Address */
ldr r1, =AT91C_BASE_CKGR
/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
ldr r0, =0x0000FF01
str r0, [r1, #CKGR_MOR]
/* Add loop to compensate Main Oscillator startup time */
ldr r0, =0x00000010
LoopOsc:
subs r0, r0, #1
bhi LoopOsc
/* scratch stack */
ldr r1, =0x00204000
/* Insure word alignment */
bic r1, r1, #3
/* Init stack SYS */
mov sp, r1
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
/*
* This does a lot more than just set up the memory, which
* is why it's called lowlevelinit
*/
bl lowlevelinit /* in memsetup.S */
bl icache_enable;
/* ------------------------------------
* Read/modify/write CP15 control register
* -------------------------------------
* read cp15 control register (cp15 r1) in r0
* ------------------------------------
*/
mrc p15, 0, r0, c1, c0, 0
/* Reset bit :Little Endian end fast bus mode */
ldr r3, =0xC0000080
/* Set bit :Asynchronous clock mode, Not Fast Bus */
ldr r4, =0xC0000000
bic r0, r0, r3
orr r0, r0, r4
/* write r0 in cp15 control register (cp15 r1) */
mcr p15, 0, r0, c1, c0, 0
#endif /* CONFIG_BOOTBINFUNC */
/*
* relocate exeception table
* relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
@ -181,19 +133,20 @@ copyex:
bne copyex
#endif
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#elif defined(CONFIG_S3C2410)
# define pWTCON 0x53000000
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
#endif
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
/* turn off the watchdog */
# if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
# define pWTCON 0x53000000
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
@ -226,25 +179,7 @@ copyex:
#endif
#ifdef CONFIG_AT91RM9200
#ifdef CONFIG_BOOTBINFUNC
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
#endif /* CONFIG_BOOTBINFUNC */
#else
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
@ -284,27 +219,6 @@ clbss_l:str r2, [r0] /* clear loop... */
cmp r0, r1
ble clbss_l
#if 0
/* try doing this stuff after the relocation */
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
*/
mov r1, #0xffffffff
ldr r0, =INTMR
str r1, [r0]
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
/* END stuff after relocation */
#endif
ldr pc, _start_armboot
_start_armboot: .word start_armboot

4
cpu/mcf523x/config.mk
View File

@ -24,4 +24,8 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
else
PLATFORM_CPPFLAGS += -m5307 -fPIC
endif

29
cpu/mcf52x2/config.mk
View File

@ -24,4 +24,33 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
is5249=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
is5253=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
is5271=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
is5272=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
is5282=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
ifneq (,$(findstring CONFIG_M5249,$(is5249)))
PLATFORM_CPPFLAGS += -mcpu=5249
endif
ifneq (,$(findstring CONFIG_M5253,$(is5253)))
PLATFORM_CPPFLAGS += -mcpu=5253
endif
ifneq (,$(findstring CONFIG_M5271,$(is5271)))
PLATFORM_CPPFLAGS += -mcpu=5271
endif
ifneq (,$(findstring CONFIG_M5272,$(is5272)))
PLATFORM_CPPFLAGS += -mcpu=5272
endif
ifneq (,$(findstring CONFIG_M5282,$(is5282)))
PLATFORM_CPPFLAGS += -mcpu=5282
endif
else
PLATFORM_CPPFLAGS += -m5307
endif

6
cpu/mcf52x2/start.S
View File

@ -58,7 +58,7 @@ _vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_R5200)
.long 0x400
#elif defined(CONFIG_M5282)
#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
@ -177,7 +177,11 @@ _after_flashbar_copy:
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
move.l #CFG_INT_FLASH_BASE, %d0
#else
move.l #CFG_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif

4
cpu/mcf532x/config.mk
View File

@ -24,4 +24,8 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
else
PLATFORM_CPPFLAGS += -m5307 -fPIC
endif

8
cpu/mcf532x/cpu.c
View File

@ -35,14 +35,10 @@ DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
wdp->cr = 0;
udelay(1000);
/* enable watchdog, set timeout to 0 and wait */
wdp->cr = WTM_WCR_EN;
while (1) ;
rcm->rcr |= RCM_RCR_SOFTRST;
/* we don't return! */
return 0;

4
cpu/mcf532x/start.S
View File

@ -131,7 +131,7 @@ _start:
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
@ -268,7 +268,7 @@ _int_handler:
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0
move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */

4
cpu/mcf5445x/config.mk
View File

@ -24,4 +24,8 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
else
PLATFORM_CPPFLAGS += -m5407 -fPIC
endif

2
cpu/mcf5445x/start.S
View File

@ -136,7 +136,7 @@ _start:
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
move.l #0, %d0

2
cpu/microblaze/cache.c
View File

@ -1,7 +1,7 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <moonstr@monstr.eu>
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.

6
cpu/microblaze/start.S
View File

@ -33,15 +33,13 @@ _start:
addi r1, r0, CFG_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
addi r6, r0, 0xb000 /* hex b000 opcode imm */
bslli r6, r6, 16 /* shift */
addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
swi r6, r0, 0x0 /* reset address */
swi r6, r0, 0x8 /* user vector exception */
swi r6, r0, 0x10 /* interrupt */
swi r6, r0, 0x20 /* hardware exception */
addi r6, r0, 0xb808 /* hew b808 opcode brai*/
bslli r6, r6, 16
addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
swi r6, r0, 0x4 /* reset address */
swi r6, r0, 0xC /* user vector exception */
swi r6, r0, 0x14 /* interrupt */

7
cpu/microblaze/timer.c
View File

@ -33,10 +33,17 @@ void reset_timer (void)
timestamp = 0;
}
#ifdef CFG_TIMER_0
ulong get_timer (ulong base)
{
return (timestamp - base);
}
#else
ulong get_timer (ulong base)
{
return (timestamp++ - base);
}
#endif
void set_timer (ulong t)
{

118
cpu/mips/au1x00_eth.c
View File

@ -90,6 +90,65 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS];
#define MAX_WAIT 1000
#if defined(CONFIG_CMD_MII)
int au1x00_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short * value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
u32 mii_control;
unsigned int timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_read busy timeout!!\n");
return -1;
}
}
mii_control = MAC_SET_MII_SELECT_REG(reg) |
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
*mii_control_reg = mii_control;
timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_read busy timeout!!\n");
return -1;
}
}
*value = *mii_data_reg;
return 0;
}
int au1x00_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
u32 mii_control;
unsigned int timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_write busy timeout!!\n");
return -1;
}
}
mii_control = MAC_SET_MII_SELECT_REG(reg) |
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
*mii_data_reg = value;
*mii_control_reg = mii_control;
return 0;
}
#endif
static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
volatile mac_fifo_t *fifo_tx =
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
@ -249,63 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
return 1;
}
#if defined(CONFIG_CMD_MII)
int au1x00_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short * value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
u32 mii_control;
unsigned int timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_read busy timeout!!\n");
return -1;
}
}
mii_control = MAC_SET_MII_SELECT_REG(reg) |
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
*mii_control_reg = mii_control;
timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_read busy timeout!!\n");
return -1;
}
}
*value = *mii_data_reg;
return 0;
}
int au1x00_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
u32 mii_control;
unsigned int timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_write busy timeout!!\n");
return;
}
}
mii_control = MAC_SET_MII_SELECT_REG(reg) |
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
*mii_data_reg = value;
*mii_control_reg = mii_control;
return 0;
}
#endif
#endif /* CONFIG_AU1X00 */

30
cpu/mips/cache.S
View File

@ -22,7 +22,6 @@
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
@ -30,13 +29,11 @@
#include <asm/addrspace.h>
#include <asm/cacheops.h>
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
/*
* cacheop macro to automate cache operations
* first some helpers...
@ -131,7 +128,6 @@ mips_cache_reset:
li t4, CFG_CACHELINE_SIZE
move t5, t4
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
@ -139,8 +135,8 @@ mips_cache_reset:
li a0, KSEG1
addu a1, a0, v0
2: sw zero, 0(a0)
2:
sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
@ -156,11 +152,11 @@ mips_cache_reset:
mtc0 zero, CP0_TAGLO
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/* Assume bottom of RAM will generate good parity for the cache.
*/
@ -201,9 +197,9 @@ mips_cache_reset:
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
j ra
.end mips_cache_reset
j ra
.end mips_cache_reset
/*******************************************************************************
*
@ -220,7 +216,7 @@ dcache_status:
andi v0, v0, 1
j ra
.end dcache_status
.end dcache_status
/*******************************************************************************
*
@ -237,11 +233,10 @@ dcache_disable:
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
mtc0 t0, CP0_CONFIG
j ra
.end dcache_disable
.end dcache_disable
/*******************************************************************************
*
@ -266,4 +261,5 @@ mips_cache_lock:
icacheop(a0,a1,a2,a3,0x1d)
j ra
.end mips_cache_lock

5
cpu/mips/config.mk
View File

@ -20,8 +20,7 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
v=$(shell \
$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
v=$(shell $(AS) --version |grep "GNU assembler" |cut -d. -f2)
MIPSFLAGS=$(shell \
if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc"; \
@ -35,6 +34,6 @@ else
ENDIANNESS = -EB
endif
MIPSFLAGS += $(ENDIANNESS) -mabicalls
MIPSFLAGS += $(ENDIANNESS)
PLATFORM_CPPFLAGS += $(MIPSFLAGS)

6
cpu/mips/cpu.c
View File

@ -39,12 +39,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
void flush_cache (ulong start_addr, ulong size)
void flush_cache(ulong start_addr, ulong size)
{
}
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
write_32bit_cp0_register(CP0_ENTRYLO1, low1);

69
cpu/mips/start.S
View File

@ -22,13 +22,11 @@
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
@ -192,7 +190,7 @@ _start:
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
@ -203,7 +201,7 @@ _start:
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
@ -234,34 +232,32 @@ reset:
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
/* Initialize GOT pointer.
*/
bal 1f
/* Initialize $gp.
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
move gp, ra
lw t1, 0(ra)
move gp, t1
.word _gp
1:
lw gp, 0(ra)
#ifdef CONFIG_INCA_IP
/* Disable INCA-IP Watchdog.
*/
la t9, disable_incaip_wdt
jalr t9
la t9, disable_incaip_wdt
jalr t9
nop
#endif
/* Initialize any external memory.
*/
la t9, lowlevel_init
jalr t9
la t9, lowlevel_init
jalr t9
nop
/* Initialize caches...
*/
la t9, mips_cache_reset
jalr t9
la t9, mips_cache_reset
jalr t9
nop
/* ... and enable them.
@ -269,12 +265,11 @@ reset:
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
la t9, mips_cache_lock
jalr t9
la t9, mips_cache_lock
jalr t9
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
@ -284,7 +279,6 @@ reset:
j t9
nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@ -298,7 +292,7 @@ reset:
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
@ -306,14 +300,14 @@ relocate_code:
move t1, a2
/*
* Fix GOT pointer:
* Fix $gp:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
* New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
@ -329,7 +323,7 @@ relocate_code:
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
@ -341,15 +335,22 @@ relocate_code:
j t0
nop
.gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
/*
* Now we want to update GOT.
*
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
lw t4, -16(t0) /* t4 <-- (_GLOBAL_OFFSET_TABLE_ - _gp) */
add t4, t4, gp /* t4 now holds _GLOBAL_OFFSET_TABLE_ */
addi t4, t4, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
@ -369,7 +370,8 @@ in_ram:
add t2, t6
sub t1, 4
1: addi t1, 4
1:
addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
@ -380,11 +382,10 @@ in_ram:
.end relocate_code
/* Exception handlers.
*/
romReserved:
b romReserved
b romReserved
romExcHandle:
b romExcHandle
b romExcHandle

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