V3s_Allwinner
/
uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 2 Wiki Activity

ARM: AM43xx: Update the base addresses of modules 

PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2013-12-10 15:02:11 +05:30 committed by Tom Rini
parent ce23b18bbb
commit 7ca1b2a210
4 changed files with 15 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -237,6 +237,14 @@ struct cm_perpll {
unsigned int cpswclkstctrl; /* offset 0x144 */ unsigned int cpswclkstctrl; /* offset 0x144 */
unsigned int lcdcclkstctrl; /* offset 0x148 */ unsigned int lcdcclkstctrl; /* offset 0x148 */
}; };
/* Encapsulating Display pll registers */
struct cm_dpll {
unsigned int resv1[2];
unsigned int clktimer2clk; /* offset 0x08 */
unsigned int resv2[10];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
#else #else
/* Encapsulating core pll registers */ /* Encapsulating core pll registers */
struct cm_wkuppll { struct cm_wkuppll {
@ -392,15 +400,12 @@ struct cm_perpll {
unsigned int resv40[7]; unsigned int resv40[7];
unsigned int cpgmac0clkctrl; /* offset 0xB20 */ unsigned int cpgmac0clkctrl; /* offset 0xB20 */
}; };
#endif /* CONFIG_AM43XX */
/* Encapsulating Display pll registers */
struct cm_dpll { struct cm_dpll {
unsigned int resv1[2]; unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x08 */ unsigned int clktimer2clk; /* offset 0x04 */
unsigned int resv2[10];
unsigned int clklcdcpixelclk; /* offset 0x34 */
}; };
#endif /* CONFIG_AM43XX */
/* Control Module RTC registers */ /* Control Module RTC registers */
struct cm_rtc { struct cm_rtc {

7
arch/arm/include/asm/arch-am33xx/hardware.h
View File

@ -48,13 +48,6 @@
#define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_0_CFG_BASE 0x4C000000
#define EMIF4_1_CFG_BASE 0x4D000000 #define EMIF4_1_CFG_BASE 0x4D000000
/* PLL related registers */
#define CM_DPLL 0x44E00500
#define CM_DEVICE 0x44E00700
#define CM_RTC 0x44E00800
#define CM_CEFUSE 0x44E00A00
#define PRM_DEVICE 0x44E00F00
/* DDR Base address */ /* DDR Base address */
#define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CTRL_ADDR 0x44E10E04
#define DDR_CONTROL_BASE_ADDR 0x44E11404 #define DDR_CONTROL_BASE_ADDR 0x44E11404

2
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
View File

@ -30,6 +30,8 @@
#define PRCM_BASE 0x44E00000 #define PRCM_BASE 0x44E00000
#define CM_PER 0x44E00000 #define CM_PER 0x44E00000
#define CM_WKUP 0x44E00400 #define CM_WKUP 0x44E00400
#define CM_DPLL 0x44E00500
#define CM_RTC 0x44E00800
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) #define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
#define PRM_RSTST (PRM_RSTCTRL + 8) #define PRM_RSTST (PRM_RSTCTRL + 8)

2
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
View File

@ -30,6 +30,8 @@
#define PRCM_BASE 0x44DF0000 #define PRCM_BASE 0x44DF0000
#define CM_WKUP 0x44DF2800 #define CM_WKUP 0x44DF2800
#define CM_PER 0x44DF8800 #define CM_PER 0x44DF8800
#define CM_DPLL 0x44DF4200
#define CM_RTC 0x44DF8500
#define PRM_RSTCTRL (PRCM_BASE + 0x4000) #define PRM_RSTCTRL (PRCM_BASE + 0x4000)
#define PRM_RSTST (PRM_RSTCTRL + 4) #define PRM_RSTST (PRM_RSTCTRL + 4)