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arm: mx6: ddr: add pd_fast_exit flag to system information 

DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit.

In slow-exit mode the DLL is off but in some quiescent state that makes it easy
to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK).
In fast-exist mode the DLL is maintained such that it is ready again in about
3tCK.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tim Harvey 2015-04-03 16:52:52 -07:00 committed by Stefano Babic
parent 32f9ef3e2b
commit 78c5a18087
2 changed files with 7 additions and 1 deletions
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7
arch/arm/cpu/armv7/mx6/ddr.c
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@ -514,17 +514,21 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* MR2 */ /* MR2 */
val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 | val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
((tcwl - 3) & 3) << 3; ((tcwl - 3) & 3) << 3;
debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
mmdc0->mdscr = MR(val, 2, 3, cs); mmdc0->mdscr = MR(val, 2, 3, cs);
/* MR3 */ /* MR3 */
debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
mmdc0->mdscr = MR(0, 3, 3, cs); mmdc0->mdscr = MR(0, 3, 3, cs);
/* MR1 */ /* MR1 */
val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 | val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
((sysinfo->rtt_nom & 2) ? 1 : 0) << 6; ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
mmdc0->mdscr = MR(val, 1, 3, cs); mmdc0->mdscr = MR(val, 1, 3, cs);
/* MR0 */ /* MR0 */
val = ((tcl - 1) << 4) | /* CAS */ val = ((tcl - 1) << 4) | /* CAS */
(1 << 8) | /* DLL Reset */ (1 << 8) | /* DLL Reset */
((twr - 3) << 9); /* Write Recovery */ ((twr - 3) << 9); /* Write Recovery */
debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
mmdc0->mdscr = MR(val, 0, 3, cs); mmdc0->mdscr = MR(val, 0, 3, cs);
/* ZQ calibration */ /* ZQ calibration */
val = (1 << 10); val = (1 << 10);
@ -535,10 +539,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
mmdc0->mdpdc = (tcke & 0x7) << 16 | mmdc0->mdpdc = (tcke & 0x7) << 16 |
5 << 12 | /* PWDT_1: 256 cycles */ 5 << 12 | /* PWDT_1: 256 cycles */
5 << 8 | /* PWDT_0: 256 cycles */ 5 << 8 | /* PWDT_0: 256 cycles */
1 << 7 | /* SLOW_PD */
1 << 6 | /* BOTH_CS_PD */ 1 << 6 | /* BOTH_CS_PD */
(tcksrx & 0x7) << 3 | (tcksrx & 0x7) << 3 |
(tcksre & 0x7); (tcksre & 0x7);
if (!sysinfo->pd_fast_exit)
mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */

1
arch/arm/include/asm/arch-mx6/mx6-ddr.h
View File

@ -250,6 +250,7 @@ struct mx6_ddr_sysinfo {
u8 mif3_mode; /* Command prediction working mode */ u8 mif3_mode; /* Command prediction working mode */
u8 rst_to_cke; /* Time from SDE enable to CKE rise */ u8 rst_to_cke; /* Time from SDE enable to CKE rise */
u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
}; };
/* /*