From ec4b73f09c384007b274b38052149025e080b138 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Fri, 20 Sep 2013 18:39:47 +0530 Subject: [PATCH 1/3] fpga: zynqpl: Add dcache flush support Buffers must be cache and dma aligned. Signed-off-by: Jagannadha Sutradharudu Teki Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 717c0394ca..f2f49b56a6 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -177,8 +177,8 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - if ((u32)buf_start & 0x3) { - u32 *new_buf = (u32 *)((u32)buf & ~0x3); + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, (u32)buf_start, (u32)new_buf, swap); @@ -284,6 +284,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); + /* flush(clean & invalidate) d-cache range buf */ + flush_dcache_range((u32)buf, (u32)buf + + roundup(bsize, ARCH_DMA_MINALIGN)); + /* Set up the transfer */ writel((u32)buf | 1, &devcfg_base->dma_src_addr); writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); From b129e8cfb07cdbbf8ce0f2a165edabeb2f7a1da7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 4 Oct 2013 10:48:59 +0200 Subject: [PATCH 2/3] fpga: zynqpl: Do not place bitstream below 1MB DMA doesn't work when src is placed below 1MB limit. Signed-off-by: Michal Simek Acked-by: Jagannadha Sutradharudu Teki --- drivers/fpga/zynqpl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index f2f49b56a6..1effbadda9 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -177,6 +178,12 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } + if ((u32)buf < SZ_1M) { + printf("%s: Bitstream has to be placed up to 1MB (%x)\n", + __func__, (u32)buf); + return FPGA_FAIL; + } + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); From 32d7cdd366a1516fa498464c261851f3a76a62ef Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 4 Oct 2013 10:51:01 +0200 Subject: [PATCH 3/3] fpga: Add support for gzip images with bitstreams Here is the set of command which has been performed to proof this feature. gzip < fpga.bin > fpga.bin.gz mkimage -A arm -O u-boot -T firmware -C gzip \ -a 20000000 -n "zc702_fpga_bin" -d fpga.bin.gz fpga.bin.gz.ub tftp 100000 fpga.bin.gz.ub fpga loadmk 0 100000 This flow should speedup loading bitstream data from external memory and save image footprint in non volatile memory. Signed-off-by: Michal Simek Acked-by: Jagannadha Sutradharudu Teki --- common/cmd_fpga.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index c4b3c8fc56..010cd24e63 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -160,9 +160,25 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) image_header_t *hdr = (image_header_t *)fpga_data; ulong data; + uint8_t comp; - data = (ulong)image_get_data(hdr); - data_size = image_get_data_size(hdr); + comp = image_get_comp(hdr); + if (comp == IH_COMP_GZIP) { + ulong image_buf = image_get_data(hdr); + data = image_get_load(hdr); + ulong image_size = ~0UL; + + if (gunzip((void *)data, ~0UL, + (void *)image_buf, + &image_size) != 0) { + puts("GUNZIP: error\n"); + return 1; + } + data_size = image_size; + } else { + data = (ulong)image_get_data(hdr); + data_size = image_get_data_size(hdr); + } rc = fpga_load(dev, (void *)data, data_size); } break;