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ppc4xx: Correct UART input clock calculation and passing to fdt 

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-10-22 10:30:38 +02:00
parent 211ea91ac6
commit 764e7417ee
2 changed files with 15 additions and 4 deletions
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4
cpu/ppc4xx/fdt.c
View File

@ -85,11 +85,7 @@ static void do_fixup_uart(void *fdt, int offset, int i, bd_t *bd)
debug("Updating node UART%d\n", i);
#if defined(CFG_EXT_SERIAL_CLOCK)
val = cpu_to_fdt32(CFG_EXT_SERIAL_CLOCK);
#else
val = cpu_to_fdt32(sys_info.freqUART);
#endif
rc = fdt_setprop(fdt, offset, "clock-frequency", &val, 4);
if (rc)
printf("Unable to update node UART, err=%s\n", fdt_strerror(rc));

15
cpu/ppc4xx/serial.c
View File

@ -528,12 +528,18 @@ int serial_init(void)
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
gd->freqUART = CFG_EXT_SERIAL_CLOCK;
#else
/* For 440, the cpu clock is on divider chain A, UART on divider
* chain B ... so cpu clock is irrelevant. Get the "optimized"
* values that are subject to the 1/2 opb clock constraint
*/
serial_divs (gd->baudrate, &udiv, &bdiv);
/* Correct UART frequency in bd-info struct now that
* the UART divisor is available
*/
gd->freqUART = gd->freqUART / udiv;
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
@ -644,6 +650,15 @@ int serial_init (void)
bdiv = (clk + tmp / 2) / tmp;
#endif /* CONFIG_405EX */
/* Correct UART frequency in bd-info struct now that
* the UART divisor is available
*/
#ifdef CFG_EXT_SERIAL_CLOCK
gd->freqUART = CFG_EXT_SERIAL_CLOCK;
#else
gd->freqUART = gd->freqUART / udiv;
#endif
out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */