ppc4xx: Maintenance patch for esd's CPCI405 derivats
-add pci_pre_init() for pci interrupt fixup code -disable phy sleep mode via reset_phy() function -use correct io accessors -cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
5a1c9ff0c4
commit
6f35c53166
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@ -23,9 +23,11 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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#include <net.h>
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -179,11 +181,15 @@ int board_early_init_f (void)
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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#ifdef CONFIG_CPCI405_6U
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if (cpci405_version() == 3) {
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mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
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} else {
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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}
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#else
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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#endif
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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@ -227,10 +233,10 @@ int cpci405_version(void)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x03000000);
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
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out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
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udelay(1000); /* wait some time before reading input */
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value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
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value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
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/*
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* Restore GPIO settings
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@ -245,7 +251,7 @@ int cpci405_version(void)
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/* CS2==0 && CS3==1 -> version 2 */
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return 2;
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case 0x00100000:
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/* CS2==1 && CS3==0 -> version 3 */
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/* CS2==1 && CS3==0 -> version 3 or 6U board */
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return 3;
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case 0x00000000:
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/* CS2==0 && CS3==0 -> version 4 */
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@ -283,7 +289,6 @@ int misc_init_r (void)
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* On CPCI-405 version 2 the environment is saved in eeprom!
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* FPGA can be gzip compressed (malloc) and booted this late.
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*/
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if (cpci405_version() >= 2) {
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/*
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* Setup GPIO pins (CS6+CS7 as GPIO)
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@ -354,6 +359,7 @@ int misc_init_r (void)
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
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udelay(1000); /* wait 1ms */
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#ifdef CONFIG_CPCI405_6U
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if (cpci405_version() == 3) {
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volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
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volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
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@ -375,6 +381,7 @@ int misc_init_r (void)
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udelay(100);
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*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
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}
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#endif
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}
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else {
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puts("\n*** U-Boot Version does not match Board Version!\n");
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@ -493,12 +500,6 @@ int checkboard (void)
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#endif
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putc ('\n');
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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return 0;
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}
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@ -511,24 +512,22 @@ long int initdram (int board_type)
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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void reset_phy(void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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#ifdef CONFIG_LXT971_NO_SLEEP
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return (0);
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_CPCI405_VER2
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@ -552,6 +551,41 @@ void ide_set_reset(int on)
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#endif /* CONFIG_CPCI405_VER2 */
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char int_line = 0xff;
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/*
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* Write pci interrupt line register (cpci405 specific)
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*/
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switch (PCI_DEV(dev) & 0x03) {
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case 0:
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int_line = 27 + 2;
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break;
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case 1:
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int_line = 27 + 3;
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break;
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case 2:
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int_line = 27 + 0;
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break;
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case 3:
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int_line = 27 + 1;
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break;
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}
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
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}
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int pci_pre_init(struct pci_controller *hose)
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{
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hose->fixup_irq = cpci405_pci_fixup_irq;
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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#ifdef CONFIG_CPCI405AB
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#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
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@ -55,6 +55,10 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_DNS | \
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@ -139,6 +143,7 @@
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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@ -37,6 +37,7 @@
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
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#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
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#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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@ -56,6 +57,10 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
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@ -166,6 +171,7 @@
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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@ -57,6 +57,10 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
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@ -150,6 +154,7 @@
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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@ -56,6 +56,10 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
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@ -171,6 +175,7 @@
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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