sh: MS7750SE support.
This adds support for the Hitachi MS7750SE. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
parent
0b135cfc2e
commit
69df3c4da0
12
Makefile
12
Makefile
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@ -2408,6 +2408,18 @@ atstk1002_config : unconfig
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#########################################################################
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#########################################################################
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#########################################################################
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## sh4 (Renesas SuperH)
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#########################################################################
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ms7750se_config: unconfig
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@ >include/config.h
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@echo "#define CONFIG_MS7750SE 1" >> include/config.h
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@./mkconfig -a $(@:_config=) sh sh4 ms7750se
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#########################################################################
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#########################################################################
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#########################################################################
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clean:
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find $(OBJTREE) -type f \
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\( -name 'core' -o -name '*.bak' -o -name '*~' \
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@ -0,0 +1,43 @@
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := ms7750se.o
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SOBJS := lowlevel_init.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#################################################################
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@ -0,0 +1,23 @@
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# NOTE: Must match value used in u-boot.lds (in this directory).
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#
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TEXT_BASE = 0x8FFC0000
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@ -0,0 +1,169 @@
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/*
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modified from SH-IPL+g
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Renesaso SuperH Solution Enginge MS775x BSC setting
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Coyright (c) 2007 Nobuhiro Iwamatsu
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#ifdef CONFIG_CPU_SUBTYPE_SH7751
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#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
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#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
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#ifdef CONFIG_MRSHPC
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#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#else /* CONFIG_MRSHPC*/
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#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#endif /* CONFIG_MRSHPC */
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#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define LED_ADDRESS 0xBA000000 /* Address of LED register */
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#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
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#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
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#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
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#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
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#define SWITCH_ADDR 0xB9000000 /* Address of DIP switches */
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#else /* CONFIG_CPU_SUBTYPE_SH7751 */
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#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
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#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
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#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:15 A0B:7 */
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#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define LED_ADDRESS 0xB0C00000 /* Address of LED register */
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#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
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#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
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#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
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#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
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#define SWITCH_ADDR 0xb0800000 /* Address of DIP switches */
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#endif /* CONFIG_CPU_SUBTYPE_SH7751 */
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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mov.l L_CCR, r1 ! CCR Address
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mov.l L_CCR_DISABLE, r0 ! CCR Data
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mov.l r0, @r1
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init_bsc:
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mov.l FRQCR_A,r1 /* FRQCR Address */
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mov.l FRQCR_D,r0 /* FRQCR Data */
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mov.w r0,@r1
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mov.l BCR1_A,r1 /* BCR1 Address */
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mov.l BCR1_D,r0 /* BCR1 Data */
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mov.l r0,@r1
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mov.l BCR2_A,r1 /* BCR2 Address */
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mov.l BCR2_D,r0 /* BCR2 Data */
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mov.w r0,@r1
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mov.l WCR1_A,r1 /* WCR1 Address */
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mov.l WCR1_D,r0 /* WCR1 Data */
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mov.l r0,@r1
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mov.l WCR2_A,r1 /* WCR2 Address */
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mov.l WCR2_D,r0 /* WCR2 Data */
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mov.l r0,@r1
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mov.l WCR3_A,r1 /* WCR3 Address */
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mov.l WCR3_D,r0 /* WCR3 Data */
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mov.l r0,@r1
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mov.l LED_A,r1 /* LED Address */
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mov #0xff,r0 /* LED ALL 'on' */
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shll8 r0
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mov.w r0,@r1
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mov.l MCR_A,r1 /* MCR Address */
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mov.l MCR_D1,r0 /* MCR Data1 */
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mov.l r0,@r1
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mov.l SDMR3_A,r1 /* Set SDRAM mode */
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mov #0,r0
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mov.b r0,@r1
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! Do you need PCMCIA setting?
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! If so, please add the lines here...
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mov.l RTCNT_A,r1 /* RTCNT Address */
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mov.l RTCNT_D,r0 /* RTCNT Data */
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mov.w r0,@r1
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mov.l RTCOR_A,r1 /* RTCOR Address */
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mov.l RTCOR_D,r0 /* RTCOR Data */
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mov.w r0,@r1
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mov.l RTCSR_A,r1 /* RTCSR Address */
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mov.l RTCSR_D,r0 /* RTCSR Data */
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mov.w r0,@r1
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mov.l RFCR_A,r1 /* RFCR Address */
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mov.l RFCR_D,r0 /* RFCR Data */
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mov.w r0,@r1 /* Clear reflesh counter */
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/* Wait DRAM refresh 30 times */
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mov #30,r3
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1:
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mov.w @r1,r0
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extu.w r0,r2
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cmp/hi r3,r2
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bf 1b
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mov.l MCR_A,r1 /* MCR Address */
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mov.l MCR_D2,r0 /* MCR Data2 */
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mov.l r0,@r1
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mov.l SDMR3_A,r1 /* Set SDRAM mode */
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mov #0,r0
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mov.b r0,@r1
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rts
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nop
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.align 2
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L_CCR: .long CCR
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L_CCR_DISABLE: .long 0x0808
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FRQCR_A: .long FRQCR
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FRQCR_D:
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#ifdef CONFIG_CPU_SUBTYPE_SH_R
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.long 0x00000e1a /* 12:3:3 */
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#else
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#ifdef CONFIG_GOOD_SESH4
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.long 0x00000e13 /* 6:2:1 */
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#else
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.long 0x00000e23 /* 6:1:1 */
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#endif
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#endif /* CONFIG_CPU_SUBTYPE_SH_R */
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BCR1_A: .long BCR1
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BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
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BCR2_A: .long BCR2
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BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
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WCR1_A: .long WCR1
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WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
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WCR2_A: .long WCR2
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WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
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WCR3_A: .long WCR3
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WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
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LED_A: .long LED_ADDRESS /* LED Address */
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RTCSR_A: .long RTCSR
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RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
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RTCNT_A: .long RTCNT
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RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
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RTCOR_A: .long RTCOR
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RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
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SDMR3_A: .long SDMR3_ADDRESS
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MCR_A: .long MCR
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MCR_D1: .long MCR_D1_VALUE
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MCR_D2: .long MCR_D2_VALUE
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RFCR_A: .long RFCR
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RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
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@ -0,0 +1,51 @@
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/*
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* Copyright (C) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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int checkboard(void)
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{
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puts("BOARD: SH7750 Solution Engine\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_memstart = CFG_SDRAM_BASE;
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gd->bd->bi_memsize = CFG_SDRAM_SIZE;
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printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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@ -0,0 +1,106 @@
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/*
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* Copyrigth (c) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
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OUTPUT_ARCH(sh)
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ENTRY(_start)
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SECTIONS
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{
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/*
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Base address of internal SDRAM is 0x0C000000.
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Although size of SDRAM can be either 16 or 32 MBytes,
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we assume 16 MBytes (ie ignore upper half if the full
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32 MBytes is present).
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NOTE: This address must match with the definition of
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TEXT_BASE in config.mk (in this directory).
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*/
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. = 0x8C000000 + (64*1024*1024) - (256*1024);
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PROVIDE (reloc_dst = .);
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PROVIDE (_ftext = .);
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PROVIDE (_fcode = .);
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PROVIDE (_start = .);
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.text :
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{
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cpu/sh4/start.o (.text)
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. = ALIGN(8192);
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common/environment.o (.ppcenv)
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. = ALIGN(8192);
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common/environment.o (.ppcenvr)
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. = ALIGN(8192);
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*(.text)
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. = ALIGN(4);
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} =0xFF
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PROVIDE (_ecode = .);
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.rodata :
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{
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*(.rodata)
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. = ALIGN(4);
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}
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PROVIDE (_etext = .);
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PROVIDE (_fdata = .);
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.data :
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{
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*(.data)
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. = ALIGN(4);
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}
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PROVIDE (_edata = .);
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PROVIDE (_fgot = .);
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.got :
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{
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*(.got)
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. = ALIGN(4);
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}
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PROVIDE (_egot = .);
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PROVIDE (__u_boot_cmd_start = .);
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.u_boot_cmd :
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{
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*(.u_boot_cmd)
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. = ALIGN(4);
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}
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PROVIDE (__u_boot_cmd_end = .);
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PROVIDE (reloc_dst_end = .);
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/* _reloc_dst_end = .; */
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PROVIDE (bss_start = .);
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PROVIDE (__bss_start = .);
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.bss :
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{
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*(.bss)
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. = ALIGN(4);
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}
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PROVIDE (bss_end = .);
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PROVIDE (_end = .);
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}
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@ -0,0 +1,75 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#undef DEBUG
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#define CONFIG_SH 1
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#define CONFIG_SH4 1
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#define CONFIG_CPU_SH7750 1
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#define CONFIG_MS7750SE 1
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#define __LITTLE_ENDIAN__ 1
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//#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NET |CFG_CMD_PING)
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#define CONFIG_COMMANDS CONFIG_CMD_DFL & ~CFG_CMD_NET
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#define CFG_SCIF_CONSOLE 1
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_CONS_SCIF1 1
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#define BOARD_LATE_INIT 1
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY -1
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#define CONFIG_BOOTARGS "console=ttySC0,115200"
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#define CONFIG_ENV_OVERWRITE 1
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#define CFG_SDRAM_BASE (0x8C000000)
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#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
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||||
|
||||
#define CFG_LONGHELP
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||||
#define CFG_PROMPT "=> "
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||||
#define CFG_CBSIZE 256
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||||
#define CFG_PBSIZE 256
|
||||
#define CFG_MAXARGS 16
|
||||
#define CFG_BARGSIZE 512
|
||||
#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } /* List of legal baudrate settings for this board */
|
||||
|
||||
#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
|
||||
#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
|
||||
|
||||
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */
|
||||
#define CFG_MONITOR_LEN (128 * 1024)
|
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
|
||||
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
#define CFG_RX_ETH_BUFFER (8)
|
||||
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#undef CFG_FLASH_CFI_BROKEN_TABLE
|
||||
#undef CFG_FLASH_QUIET_TEST
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CFG_FLASH_BASE (0xA1000000)
|
||||
#define CFG_MAX_FLASH_BANKS (1) /* Max number of
|
||||
* Flash memory banks
|
||||
*/
|
||||
#define CFG_MAX_FLASH_SECT 142
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
#define CFG_FLASH_ERASE_TOUT 120000
|
||||
#define CFG_FLASH_WRITE_TOUT 500
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#define TMU_CLK_DIVIDER 4
|
||||
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
|
||||
#define CFG_PLL_SETTLING_TIME 100 /* in us */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue