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Fix mx31_decode_pll 

The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau 2012-08-14 08:43:47 +00:00 committed by Stefano Babic
parent 543d247935
commit 697191d57f
1 changed files with 5 additions and 3 deletions
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8
arch/arm/cpu/arm1136/mx31/generic.c
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@ -22,6 +22,7 @@
*/ */
#include <common.h> #include <common.h>
#include <div64.h>
#include <asm/arch/imx-regs.h> #include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/io.h> #include <asm/io.h>
@ -30,16 +31,17 @@
static u32 mx31_decode_pll(u32 reg, u32 infreq) static u32 mx31_decode_pll(u32 reg, u32 infreq)
{ {
u32 mfi = GET_PLL_MFI(reg); u32 mfi = GET_PLL_MFI(reg);
u32 mfn = GET_PLL_MFN(reg); s32 mfn = GET_PLL_MFN(reg);
u32 mfd = GET_PLL_MFD(reg); u32 mfd = GET_PLL_MFD(reg);
u32 pd = GET_PLL_PD(reg); u32 pd = GET_PLL_PD(reg);
mfi = mfi <= 5 ? 5 : mfi; mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1; mfd += 1;
pd += 1; pd += 1;
return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
(mfd * pd)) << 10; mfd * pd);
} }
static u32 mx31_get_mpl_dpdgck_clk(void) static u32 mx31_get_mpl_dpdgck_clk(void)