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socfpga: Creating driver for Reset Manager 

Consolidating reset code into reset_manager.c. Also
separating reset configuration for virtual target and
real hardware Cyclone V development kit

Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
This commit is contained in:
Chin Liang See 2013-08-07 10:08:03 -05:00 committed by Albert ARIBAUD
parent 31ad864e47
commit 68e1747f9c
4 changed files with 47 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/cpu/armv7/socfpga/Makefile
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@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
COBJS-y := misc.o timer.o
COBJS-y := misc.o timer.o reset_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)

27
arch/arm/cpu/armv7/socfpga/misc.c
View File

@ -6,36 +6,9 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
/*
* Write the reset manager register to cause reset
*/
void reset_cpu(ulong addr)
{
/* request a warm reset */
writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
/*
* infinite loop here as watchdog will trigger and reset
* the processor
*/
while (1)
;
}
/*
* Release peripherals from reset based on handoff
*/
void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per_mod_reset);
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);

39
arch/arm/cpu/armv7/socfpga/reset_manager.c Normal file
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@ -0,0 +1,39 @@
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
/*
* Write the reset manager register to cause reset
*/
void reset_cpu(ulong addr)
{
/* request a warm reset */
writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
&reset_manager_base->ctrl);
/*
* infinite loop here as watchdog will trigger and reset
* the processor
*/
while (1)
;
}
/*
* Release peripherals from reset based on handoff
*/
void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per_mod_reset);
}

10
arch/arm/include/asm/arch-socfpga/reset_manager.h
View File

@ -11,16 +11,20 @@ void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
struct socfpga_reset_manager {
u32 padding1;
u32 status;
u32 ctrl;
u32 padding2;
u32 padding3;
u32 counts;
u32 padding1;
u32 mpu_mod_reset;
u32 per_mod_reset;
u32 per2_mod_reset;
u32 brg_mod_reset;
};
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
#else
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif
#endif /* _RESET_MANAGER_H_ */