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uboot
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Merge branch 'master' of git://git.denx.de/u-boot-usb

This commit is contained in:
Tom Rini 2014-11-11 16:59:25 -05:00
parent 63f7af9a4c 6a559bbe2f
commit 6841deb620
16 changed files with 186 additions and 78 deletions
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21
board/altera/socfpga/socfpga_cyclone5.c
View File

@ -8,6 +8,10 @@
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <usb.h>
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@ -39,3 +43,20 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
int board_usb_init(int index, enum usb_init_type init)
{
return s3c_udc_probe(&socfpga_otg_data);
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;
}
#endif

7
common/usb_storage.c
View File

@ -1351,8 +1351,11 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss,
perq = usb_stor_buf[0];
modi = usb_stor_buf[1];
if ((perq & 0x1f) == 0x1f) {
/* skip unknown devices */
/*
* Skip unknown devices (0x1f) and enclosure service devices (0x0d),
* they would not respond to test_unit_ready .
*/
if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) {
return 0;
}
if ((modi&0x80) == 0x80) {

4
drivers/usb/eth/Makefile
View File

@ -5,8 +5,6 @@
# new USB host ethernet layer dependencies
obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
ifdef CONFIG_USB_ETHER_ASIX
obj-y += asix.o
endif
obj-$(CONFIG_USB_ETHER_ASIX) += asix.o
obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o

1
drivers/usb/gadget/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
ifdef CONFIG_USB_GADGET
obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
obj-$(CONFIG_CI_UDC) += ci_udc.o
obj-$(CONFIG_THOR_FUNCTION) += f_thor.o

79
drivers/usb/gadget/s3c_udc_otg.c
View File

@ -31,7 +31,6 @@
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/gpio.h>
#include "regs-otg.h"
#include <usb/lin_gadget_compat.h>
@ -105,7 +104,7 @@ static void stop_activity(struct s3c_udc *dev,
struct usb_gadget_driver *driver);
static int udc_enable(struct s3c_udc *dev);
static void udc_set_address(struct s3c_udc *dev, unsigned char address);
static void reconfig_usbd(void);
static void reconfig_usbd(struct s3c_udc *dev);
static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
static void nuke(struct s3c_ep *ep, int status);
static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
@ -146,68 +145,14 @@ static struct usb_ep_ops s3c_ep_ops = {
void __iomem *regs_otg;
struct s3c_usbotg_reg *reg;
struct s3c_usbotg_phy *phy;
static unsigned int usb_phy_ctrl;
bool dfu_usb_get_reset(void)
{
return !!(readl(&reg->gintsts) & INT_RESET);
}
void otg_phy_init(struct s3c_udc *dev)
{
dev->pdata->phy_control(1);
/*USB PHY0 Enable */
printf("USB PHY0 Enable\n");
/* Enable PHY */
writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
writel((readl(&phy->phypwr)
&~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
&~FORCE_SUSPEND_0), &phy->phypwr);
else /* C110 GONI */
writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
&~FORCE_SUSPEND_0), &phy->phypwr);
if (s5p_cpu_id == 0x4412)
writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
&phy->phyclk); /* PLL 24Mhz */
else
writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
| PHY_SW_RST0, &phy->rstcon);
udelay(10);
writel(readl(&phy->rstcon)
&~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
udelay(10);
}
void otg_phy_off(struct s3c_udc *dev)
{
/* reset controller just in case */
writel(PHY_SW_RST0, &phy->rstcon);
udelay(20);
writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
udelay(20);
writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
| FORCE_SUSPEND_0, &phy->phypwr);
writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
&phy->phyclk);
udelay(10000);
dev->pdata->phy_control(0);
}
__weak void otg_phy_init(struct s3c_udc *dev) {}
__weak void otg_phy_off(struct s3c_udc *dev) {}
/***********************************************************/
@ -270,7 +215,7 @@ static int udc_enable(struct s3c_udc *dev)
debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
otg_phy_init(dev);
reconfig_usbd();
reconfig_usbd(dev);
debug_cond(DEBUG_SETUP != 0,
"S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
@ -451,15 +396,17 @@ static void stop_activity(struct s3c_udc *dev,
udc_reinit(dev);
}
static void reconfig_usbd(void)
static void reconfig_usbd(struct s3c_udc *dev)
{
/* 2. Soft-reset OTG Core and then unreset again. */
int i;
unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
uint32_t dflt_gusbcfg;
debug("Reseting OTG controller\n");
writel(0<<15 /* PHY Low Power Clock sel*/
dflt_gusbcfg =
0<<15 /* PHY Low Power Clock sel*/
|1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
|0x5<<10 /* Turnaround time*/
|0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
@ -468,8 +415,12 @@ static void reconfig_usbd(void)
|0<<6 /* 0: high speed utmi+, 1: full speed serial*/
|0<<4 /* 0: utmi+, 1:ulpi*/
|1<<3 /* phy i/f 0:8bit, 1:16bit*/
|0x7<<0, /* HS/FS Timeout**/
&reg->gusbcfg);
|0x7<<0; /* HS/FS Timeout**/
if (dev->pdata->usb_gusbcfg)
dflt_gusbcfg = dev->pdata->usb_gusbcfg;
writel(dflt_gusbcfg, &reg->gusbcfg);
/* 3. Put the OTG device core in the disconnected state.*/
uTemp = readl(&reg->dctl);
@ -854,9 +805,7 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
dev->pdata = pdata;
phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
usb_phy_ctrl = pdata->usb_phy_ctrl;
/* regs_otg = (void *)pdata->regs_otg; */

101
drivers/usb/gadget/s3c_udc_otg_phy.c Normal file
View File

@ -0,0 +1,101 @@
/*
* drivers/usb/gadget/s3c_udc_otg.c
* Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
*
* Copyright (C) 2008 for Samsung Electronics
*
* BSP Support for Samsung's UDC driver
* available at:
* git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
*
* State machine bugfixes:
* Marek Szyprowski <m.szyprowski@samsung.com>
*
* Ported to u-boot:
* Marek Szyprowski <m.szyprowski@samsung.com>
* Lukasz Majewski <l.majewski@samsumg.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/errno.h>
#include <linux/list.h>
#include <malloc.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include "regs-otg.h"
#include <usb/lin_gadget_compat.h>
#include <usb/s3c_udc.h>
void otg_phy_init(struct s3c_udc *dev)
{
unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
struct s3c_usbotg_phy *phy =
(struct s3c_usbotg_phy *)dev->pdata->regs_phy;
dev->pdata->phy_control(1);
/* USB PHY0 Enable */
printf("USB PHY0 Enable\n");
/* Enable PHY */
writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
writel((readl(&phy->phypwr)
&~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
&~FORCE_SUSPEND_0), &phy->phypwr);
else /* C110 GONI */
writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
&~FORCE_SUSPEND_0), &phy->phypwr);
if (s5p_cpu_id == 0x4412)
writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
&phy->phyclk); /* PLL 24Mhz */
else
writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
| PHY_SW_RST0, &phy->rstcon);
udelay(10);
writel(readl(&phy->rstcon)
&~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
udelay(10);
}
void otg_phy_off(struct s3c_udc *dev)
{
unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
struct s3c_usbotg_phy *phy =
(struct s3c_usbotg_phy *)dev->pdata->regs_phy;
/* reset controller just in case */
writel(PHY_SW_RST0, &phy->rstcon);
udelay(20);
writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
udelay(20);
writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
| FORCE_SUSPEND_0, &phy->phypwr);
writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
&phy->phyclk);
udelay(10000);
dev->pdata->phy_control(0);
}

2
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
View File

@ -551,7 +551,7 @@ static int s3c_udc_irq(int irq, void *_dev)
debug_cond(DEBUG_ISR,
"\t\tOTG core got reset (%d)!!\n",
reset_available);
reconfig_usbd();
reconfig_usbd(dev);
dev->ep0state = WAIT_FOR_SETUP;
reset_available = 0;
s3c_udc_pre_setup();

8
drivers/usb/host/ehci-rmobile.c
View File

@ -13,18 +13,18 @@
#include "ehci.h"
#if defined(CONFIG_R8A7740)
static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
static u32 usb_base_address[] = {
0xC6700000
};
#elif defined(CONFIG_R8A7790)
static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
static u32 usb_base_address[] = {
0xEE080000, /* USB0 (EHCI) */
0xEE0A0000, /* USB1 */
0xEE0C0000, /* USB2 */
};
#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
defined(CONFIG_R8A7794)
static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
static u32 usb_base_address[] = {
0xEE080000, /* USB0 (EHCI) */
0xEE0C0000, /* USB1 */
};
@ -53,7 +53,7 @@ int ehci_hcd_stop(int index)
if (!i)
printf("error : ehci(%d) reset failed.\n", index);
if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1))
if (index == (ARRAY_SIZE(usb_base_address) - 1))
setbits_le32(SMSTPCR7, SMSTPCR703);
return 0;

4
drivers/usb/host/ehci.h
View File

@ -47,9 +47,9 @@ struct ehci_hcor {
uint32_t or_usbcmd;
#define CMD_PARK (1 << 11) /* enable "park" */
#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
#define CMD_ASE (1 << 5) /* async schedule enable */
#define CMD_LRESET (1 << 7) /* partial reset */
#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */
#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
#define CMD_ASE (1 << 5) /* async schedule enable */
#define CMD_PSE (1 << 4) /* periodic schedule enable */
#define CMD_RESET (1 << 1) /* reset HC not bus */
#define CMD_RUN (1 << 0) /* start/stop HC */

1
include/configs/exynos4-common.h
View File

@ -59,6 +59,7 @@
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2

1
include/configs/s5p_goni.h
View File

@ -281,6 +281,7 @@
#define CONFIG_SYS_MAX_I2C_BUS 7
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_USB_MASS_STORAGE

1
include/configs/s5pc210_universal.h
View File

@ -181,6 +181,7 @@
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
/*

1
include/configs/smdkv310.h
View File

@ -14,6 +14,7 @@
#undef CONFIG_BOARD_COMMON
#undef CONFIG_USB_GADGET
#undef CONFIG_USB_GADGET_S3C_UDC_OTG
#undef CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
#undef CONFIG_CMD_USB_MASS_STORAGE
#undef CONFIG_REVISION_TAG
#undef CONFIG_CMD_THOR_DOWNLOAD

30
include/configs/socfpga_common.h
View File

@ -37,7 +37,7 @@
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x0
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
@ -171,6 +171,34 @@
*/
#endif
/*
* USB Gadget (DFU, UMS)
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
#ifndef CONFIG_G_DNL_MANUFACTURER
#define CONFIG_G_DNL_MANUFACTURER "Altera"
#endif
#endif
/*
* U-Boot environment
*/

2
include/usb.h
View File

@ -11,6 +11,8 @@
#include <usb_defs.h>
#include <linux/usb/ch9.h>
#include <asm/cache.h>
#include <part.h>
/*
* The EHCI spec says that we must align to at least 32 bytes. However,

1
include/usb/s3c_udc.h
View File

@ -108,5 +108,6 @@ struct s3c_plat_otg_data {
unsigned int regs_otg;
unsigned int usb_phy_ctrl;
unsigned int usb_flags;
unsigned int usb_gusbcfg;
};
#endif