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85xx: Limit CPU2 workaround to parts that have the errata 

Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Andy Fleming 2008-05-07 16:54:31 -05:00 committed by Andrew Fleming-AFLEMING
parent 908261f3fd
commit 66f5fa9263
1 changed files with 6 additions and 1 deletions
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7
board/freescale/mpc8548cds/mpc8548cds.c
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@ -59,6 +59,7 @@ int checkboard (void)
uint pci_slot = get_pci_slot (); uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision (); uint cpu_board_rev = get_cpu_board_revision ();
uint svr;
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot); get_board_version (), pci_slot);
@ -71,12 +72,16 @@ int checkboard (void)
*/ */
local_bus_init (); local_bus_init ();
svr = get_svr();
/* /*
* Fix CPU2 errata: A core hang possible while executing a * Fix CPU2 errata: A core hang possible while executing a
* msync instruction and a snoopable transaction from an I/O * msync instruction and a snoopable transaction from an I/O
* master tagged to make quick forward progress is present. * master tagged to make quick forward progress is present.
* Fixed in Silicon Rev.2.1
*/ */
ecm->eebpcr |= (1 << 16); if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
ecm->eebpcr |= (1 << 16);
/* /*
* Hack TSEC 3 and 4 IO voltages. * Hack TSEC 3 and 4 IO voltages.