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mx5 clocks: Add and use CCSR definitions 

This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau 2012-09-27 10:22:22 +00:00 committed by Tom Rini
parent 414e1660c8
commit 649dc8abd9
2 changed files with 46 additions and 11 deletions
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34
arch/arm/cpu/armv7/mx5/clock.c
View File

@ -36,7 +36,9 @@ enum pll_clocks {
PLL1_CLOCK = 0,
PLL2_CLOCK,
PLL3_CLOCK,
#ifdef CONFIG_MX53
PLL4_CLOCK,
#endif
PLL_CLOCKS,
};
@ -323,10 +325,10 @@ static u32 get_lp_apm(void)
u32 ret_val = 0;
u32 ccsr = readl(&mxc_ccm->ccsr);
if (((ccsr >> 9) & 1) == 0)
ret_val = MXC_HCLK;
else
if (ccsr & MXC_CCM_CCSR_LP_APM)
ret_val = MXC_CLK32 * 1024;
else
ret_val = MXC_HCLK;
return ret_val;
}
@ -593,40 +595,50 @@ static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
switch (index) {
case PLL1_CLOCK:
/* Switch ARM to PLL2 clock */
writel(ccsr | 0x4, &mxc_ccm->ccsr);
writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
&mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
writel(ccsr & ~0x4, &mxc_ccm->ccsr);
writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
&mxc_ccm->ccsr);
break;
case PLL2_CLOCK:
/* Switch to pll2 bypass clock */
writel(ccsr | 0x2, &mxc_ccm->ccsr);
writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
&mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
writel(ccsr & ~0x2, &mxc_ccm->ccsr);
writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
&mxc_ccm->ccsr);
break;
case PLL3_CLOCK:
/* Switch to pll3 bypass clock */
writel(ccsr | 0x1, &mxc_ccm->ccsr);
writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
&mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
writel(ccsr & ~0x1, &mxc_ccm->ccsr);
writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
&mxc_ccm->ccsr);
break;
#ifdef CONFIG_MX53
case PLL4_CLOCK:
/* Switch to pll4 bypass clock */
writel(ccsr | 0x20, &mxc_ccm->ccsr);
writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
&mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
writel(ccsr & ~0x20, &mxc_ccm->ccsr);
writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
&mxc_ccm->ccsr);
break;
#endif
default:
return -EINVAL;
}

23
arch/arm/include/asm/arch-mx5/crm_regs.h
View File

@ -82,6 +82,29 @@ struct mxc_ccm_reg {
u32 cmeor;
};
/* Define the bits in register CCSR */
#if defined(CONFIG_MX51)
#define MXC_CCM_CCSR_LP_APM (0x1 << 9)
#elif defined(CONFIG_MX53)
#define MXC_CCM_CCSR_LP_APM (0x1 << 10)
#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9)
#endif
#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7
#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7)
#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3)
#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5
#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5)
#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5)
#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3)
#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3
#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3)
#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3)
#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3)
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2)
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1)
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7