x86: Enable mrc cache for bayleybay and minnowmax
Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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@ -68,9 +68,15 @@
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#size-cells = <0>;
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compatible = "intel,ich-spi";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "winbond,w25q64dw", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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rw-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x006e0000 0x00010000>;
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};
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};
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};
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@ -273,9 +273,15 @@
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#size-cells = <0>;
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compatible = "intel,ich-spi";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "stmicro,n25q064a", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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rw-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x006f0000 0x00010000>;
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};
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};
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};
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@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y
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CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
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CONFIG_TARGET_BAYLEYBAY=y
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CONFIG_HAVE_INTEL_ME=y
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CONFIG_ENABLE_MRC_CACHE=y
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CONFIG_SMP=y
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CONFIG_HAVE_VGA_BIOS=y
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CONFIG_VGA_BIOS_ADDR=0xfffa0000
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@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y
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CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
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CONFIG_TARGET_MINNOWMAX=y
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CONFIG_HAVE_INTEL_ME=y
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CONFIG_ENABLE_MRC_CACHE=y
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CONFIG_SMP=y
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CONFIG_HAVE_VGA_BIOS=y
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CONFIG_GENERATE_PIRQ_TABLE=y
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@ -190,6 +190,7 @@ Offset Description Controlling config
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000000 descriptor.bin Hard-coded to 0 in ifdtool
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001000 me.bin Set by the descriptor
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500000 <spare>
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6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
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700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
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790000 vga.bin CONFIG_VGA_BIOS_ADDR
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7c0000 fsp.bin CONFIG_FSP_ADDR
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