mpc83xx: cosmetic: sbc8349.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
80ae4df929
commit
60e1dc151e
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@ -114,7 +114,9 @@
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* NB: manual DDR setup untested on sbc834x
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*/
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
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#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_10)
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#define CONFIG_SYS_DDR_TIMING_1 0x36332321
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#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
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#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
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@ -122,10 +124,12 @@
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#if defined(CONFIG_DDR_32BIT)
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/* set burst length to 8 for 32-bit data path */
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#define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
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/* DLL,normal,seq,4/2.5, 8 burst len */
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#define CONFIG_SYS_DDR_MODE 0x00000023
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#else
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/* the default burst length is 4 - for 64-bit data path */
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#define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
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/* DLL,normal,seq,4/2.5, 4 burst len */
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#define CONFIG_SYS_DDR_MODE 0x00000022
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#endif
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#endif
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@ -144,12 +148,13 @@
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#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
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/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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| (2 << BR_PS_SHIFT) /* 16 bit port */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
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/* window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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@ -168,10 +173,13 @@
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#endif
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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/* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
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/* Size of used area in RAM*/
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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@ -209,7 +217,8 @@
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* FIXME: the top 17 bits of BR2.
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*/
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#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
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/* Port-size=32bit, MSEL=SDRAM */
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#define CONFIG_SYS_BR2_PRELIM 0xF0001861
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#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
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#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
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@ -229,18 +238,19 @@
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#define CONFIG_SYS_OR2_PRELIM 0xFC006901
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#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
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/* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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/* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \
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#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
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| LSDMR_BSMA1516 \
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| LSDMR_RFCR8 \
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| LSDMR_PRETOACT6 \
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| LSDMR_ACTTORW3 \
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| LSDMR_BL8 \
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| LSDMR_WRC3 \
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| LSDMR_CL3 \
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)
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| LSDMR_CL3)
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/*
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* SDRAM Controller configuration sequence.
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@ -262,7 +272,7 @@
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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@ -439,9 +449,11 @@
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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@ -449,7 +461,8 @@
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
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@ -502,7 +515,7 @@
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_TSEC1M_IN_GMII |\
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HRCWH_TSEC2M_IN_GMII )
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HRCWH_TSEC2M_IN_GMII)
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#else
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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@ -515,7 +528,7 @@
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_TSEC1M_IN_GMII |\
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HRCWH_TSEC2M_IN_GMII )
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HRCWH_TSEC2M_IN_GMII)
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#endif
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/* System IO Config */
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@ -523,13 +536,13 @@
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#define CONFIG_SYS_SICRL SICRL_LDP_A
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE)
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
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| HID0_ENABLE_INSTRUCTION_CACHE)
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/* #define CONFIG_SYS_HID0_FINAL (\
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HID0_ENABLE_INSTRUCTION_CACHE |\
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HID0_ENABLE_M_BIT |\
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HID0_ENABLE_ADDRESS_BROADCAST ) */
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HID0_ENABLE_ADDRESS_BROADCAST) */
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#define CONFIG_SYS_HID2 HID2_HBE
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@ -537,15 +550,31 @@
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR @ 0x00000000 */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* PCI @ 0x80000000 */
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#ifdef CONFIG_PCI
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#else
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#define CONFIG_SYS_IBAT1L (0)
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#define CONFIG_SYS_IBAT1U (0)
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@ -554,10 +583,21 @@
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#endif
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#ifdef CONFIG_MPC83XX_PCI2
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#else
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#define CONFIG_SYS_IBAT3L (0)
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#define CONFIG_SYS_IBAT3U (0)
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@ -566,12 +606,20 @@
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#endif
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/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
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#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT6L (0xF0000000 \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT7L (0)
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@ -613,7 +661,8 @@
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#define CONFIG_ROOTPATH "/tftpboot/rootfs"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 800000
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#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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@ -647,7 +696,8 @@
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
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"$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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