drivers: pinctrl: Add pinctrl driver for Microchip PIC32.
In PIC32 pin-controller is a combined gpio-controller, pin-mux and pin-config module. Remappable peripherals are assigned pins through per-pin based muxing logic. And pin configuration are performed on specific port registers which are shared along with gpio controller. Note, non-remappable peripherals have default pins assigned thus require no muxing. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Purna Chandra Mandal
Daniel Schwierzeck
parent
a0e7908326
commit
5f266c60bf
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@ -131,6 +131,16 @@ config PINCTRL_SANDBOX
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actually does nothing but print debug messages when pinctrl
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operations are invoked.
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config PIC32_PINCTRL
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bool "Microchip PIC32 pin-control and pin-mux driver"
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depends on DM && MACH_PIC32
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default y
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help
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Supports individual pin selection and configuration for each remappable
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peripheral available on Microchip PIC32 SoCs. This driver is controlled
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by a device tree node which contains both GPIO defintion and pin control
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functions.
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endif
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source "drivers/pinctrl/uniphier/Kconfig"
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@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
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obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
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obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
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@ -0,0 +1,363 @@
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/*
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* Pinctrl driver for Microchip PIC32 SoCs
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* Copyright (c) 2015 Microchip Technology Inc.
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* Written by Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <mach/pic32.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* PIC32 has 10 peripheral ports with 16 pins each.
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* Ports are marked PORTA-PORTK or PORT0-PORT9.
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*/
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enum {
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PIC32_PORT_A = 0,
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PIC32_PORT_B = 1,
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PIC32_PORT_C = 2,
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PIC32_PORT_D = 3,
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PIC32_PORT_E = 4,
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PIC32_PORT_F = 5,
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PIC32_PORT_G = 6,
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PIC32_PORT_H = 7,
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PIC32_PORT_J = 8, /* no PORT_I */
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PIC32_PORT_K = 9,
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PIC32_PINS_PER_PORT = 16,
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};
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#define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
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#define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2)
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/* pin configuration descriptor */
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struct pic32_pin_config {
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u16 port; /* port number */
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u16 pin; /* pin number in the port */
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u32 config; /* one of PIN_CONFIG_* */
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};
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#define PIN_CONFIG(_prt, _pin, _cfg) \
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{.port = (_prt), .pin = (_pin), .config = (_cfg), }
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/* In PIC32 muxing is performed at pin-level through two
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* different set of registers - one set for input functions,
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* and other for output functions.
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* Pin configuration is handled through port register.
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*/
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/* Port control registers */
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struct pic32_reg_port {
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struct pic32_reg_atomic ansel;
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struct pic32_reg_atomic tris;
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struct pic32_reg_atomic port;
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struct pic32_reg_atomic lat;
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struct pic32_reg_atomic odc;
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struct pic32_reg_atomic cnpu;
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struct pic32_reg_atomic cnpd;
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struct pic32_reg_atomic cncon;
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struct pic32_reg_atomic unused[8];
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};
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/* Input function mux registers */
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struct pic32_reg_in_mux {
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u32 unused0;
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u32 int1[4];
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u32 unused1;
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u32 t2ck[8];
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u32 ic1[9];
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u32 unused2;
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u32 ocfar;
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u32 unused3;
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u32 u1rx;
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u32 u1cts;
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u32 u2rx;
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u32 u2cts;
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u32 u3rx;
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u32 u3cts;
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u32 u4rx;
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u32 u4cts;
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u32 u5rx;
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u32 u5cts;
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u32 u6rx;
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u32 u6cts;
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u32 unused4;
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u32 sdi1;
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u32 ss1;
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u32 unused5;
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u32 sdi2;
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u32 ss2;
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u32 unused6;
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u32 sdi3;
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u32 ss3;
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u32 unused7;
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u32 sdi4;
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u32 ss4;
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u32 unused8;
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u32 sdi5;
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u32 ss5;
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u32 unused9;
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u32 sdi6;
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u32 ss6;
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u32 c1rx;
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u32 c2rx;
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u32 refclki1;
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u32 refclki2;
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u32 refclki3;
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u32 refclki4;
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};
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/* output mux register offset */
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#define PPS_OUT(__port, __pin) \
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(((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)
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struct pic32_pinctrl_priv {
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struct pic32_reg_in_mux *mux_in; /* mux input function */
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struct pic32_reg_port *pinconf; /* pin configuration*/
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void __iomem *mux_out; /* mux output function */
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};
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enum {
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PERIPH_ID_UART1,
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PERIPH_ID_UART2,
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PERIPH_ID_ETH,
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PERIPH_ID_USB,
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PERIPH_ID_SDHCI,
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PERIPH_ID_I2C1,
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PERIPH_ID_I2C2,
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PERIPH_ID_SPI1,
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PERIPH_ID_SPI2,
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PERIPH_ID_SQI,
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};
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static int pic32_pinconfig_one(struct pic32_pinctrl_priv *priv,
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u32 port_nr, u32 pin, u32 param)
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{
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struct pic32_reg_port *port;
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port = &priv->pinconf[port_nr];
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switch (param) {
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case PIN_CONFIG_PIC32_DIGITAL:
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writel(BIT(pin), &port->ansel.clr);
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break;
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case PIN_CONFIG_PIC32_ANALOG:
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writel(BIT(pin), &port->ansel.set);
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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writel(BIT(pin), &port->tris.set);
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break;
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case PIN_CONFIG_OUTPUT:
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writel(BIT(pin), &port->tris.clr);
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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writel(BIT(pin), &port->cnpu.set);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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writel(BIT(pin), &port->cnpd.set);
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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writel(BIT(pin), &port->odc.set);
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break;
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default:
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break;
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}
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return 0;
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}
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static int pic32_pinconfig_set(struct pic32_pinctrl_priv *priv,
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const struct pic32_pin_config *list, int count)
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{
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int i;
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for (i = 0 ; i < count; i++)
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pic32_pinconfig_one(priv, list[i].port,
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list[i].pin, list[i].config);
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return 0;
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}
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static void pic32_eth_pin_config(struct udevice *dev)
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{
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struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
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const struct pic32_pin_config configs[] = {
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/* EMDC - D11 */
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PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_OUTPUT),
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/* ETXEN */
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PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_OUTPUT),
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/* ECRSDV */
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PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_INPUT_ENABLE),
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/* ERXD0 */
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PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_INPUT_ENABLE),
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PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_BIAS_PULL_DOWN),
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/* ERXD1 */
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PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_INPUT_ENABLE),
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PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_BIAS_PULL_DOWN),
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/* EREFCLK */
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PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_INPUT_ENABLE),
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/* ETXD1 */
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PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_OUTPUT),
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/* ETXD0 */
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PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_OUTPUT),
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/* EMDIO */
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PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_INPUT_ENABLE),
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/* ERXERR */
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PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_PIC32_DIGITAL),
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PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_INPUT_ENABLE),
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};
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pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
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}
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static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
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{
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struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
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switch (func) {
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case PERIPH_ID_UART2:
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/* PPS for U2 RX/TX */
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writel(0x02, priv->mux_out + PPS_OUT(PIC32_PORT_G, 9));
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writel(0x05, &priv->mux_in->u2rx); /* B0 */
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/* set digital mode */
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pic32_pinconfig_one(priv, PIC32_PORT_G, 9,
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PIN_CONFIG_PIC32_DIGITAL);
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pic32_pinconfig_one(priv, PIC32_PORT_B, 0,
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PIN_CONFIG_PIC32_DIGITAL);
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break;
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case PERIPH_ID_ETH:
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pic32_eth_pin_config(dev);
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break;
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default:
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debug("%s: unknown-unhandled case\n", __func__);
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break;
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}
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return 0;
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}
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static int pic32_pinctrl_get_periph_id(struct udevice *dev,
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struct udevice *periph)
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{
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int ret;
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u32 cell[2];
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ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
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"interrupts", cell, ARRAY_SIZE(cell));
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if (ret < 0)
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return -EINVAL;
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/* interrupt number */
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switch (cell[0]) {
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case 112 ... 114:
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return PERIPH_ID_UART1;
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case 145 ... 147:
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return PERIPH_ID_UART2;
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case 109 ... 111:
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return PERIPH_ID_SPI1;
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case 142 ... 144:
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return PERIPH_ID_SPI2;
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case 115 ... 117:
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return PERIPH_ID_I2C1;
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case 148 ... 150:
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return PERIPH_ID_I2C2;
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case 132 ... 133:
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return PERIPH_ID_USB;
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case 169:
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return PERIPH_ID_SQI;
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case 191:
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return PERIPH_ID_SDHCI;
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case 153:
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return PERIPH_ID_ETH;
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default:
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break;
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}
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return -ENOENT;
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}
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static int pic32_pinctrl_set_state_simple(struct udevice *dev,
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struct udevice *periph)
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{
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int func;
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debug("%s: periph %s\n", __func__, periph->name);
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func = pic32_pinctrl_get_periph_id(dev, periph);
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if (func < 0)
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return func;
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return pic32_pinctrl_request(dev, func, 0);
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}
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static struct pinctrl_ops pic32_pinctrl_ops = {
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.set_state_simple = pic32_pinctrl_set_state_simple,
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.request = pic32_pinctrl_request,
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.get_periph_id = pic32_pinctrl_get_periph_id,
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};
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static int pic32_pinctrl_probe(struct udevice *dev)
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{
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struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
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struct fdt_resource res;
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void *fdt = (void *)gd->fdt_blob;
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int node = dev->of_offset;
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int ret;
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"ppsin", &res);
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if (ret < 0) {
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printf("pinctrl: resource \"ppsin\" not found\n");
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return ret;
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}
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priv->mux_in = ioremap(res.start, fdt_resource_size(&res));
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"ppsout", &res);
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if (ret < 0) {
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printf("pinctrl: resource \"ppsout\" not found\n");
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return ret;
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}
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priv->mux_out = ioremap(res.start, fdt_resource_size(&res));
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"port", &res);
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if (ret < 0) {
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printf("pinctrl: resource \"port\" not found\n");
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return ret;
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}
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priv->pinconf = ioremap(res.start, fdt_resource_size(&res));
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return 0;
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}
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static int pic32_pinctrl_bind(struct udevice *dev)
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{
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/* scan child GPIO banks */
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return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
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}
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static const struct udevice_id pic32_pinctrl_ids[] = {
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{ .compatible = "microchip,pic32mzda-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_pic32) = {
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.name = "pinctrl_pic32",
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.id = UCLASS_PINCTRL,
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.of_match = pic32_pinctrl_ids,
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.ops = &pic32_pinctrl_ops,
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.probe = pic32_pinctrl_probe,
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.bind = pic32_pinctrl_bind,
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.priv_auto_alloc_size = sizeof(struct pic32_pinctrl_priv),
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};
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