Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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@ -26,10 +26,6 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/clk.h>
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#ifndef CONFIG_SYS_CLK_FREQ_C210
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#define CONFIG_SYS_CLK_FREQ_C210 24000000
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#endif
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/* exynos4: return pll clock frequency */
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/* exynos4: return pll clock frequency */
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static unsigned long exynos4_get_pll_clk(int pllreg)
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static unsigned long exynos4_get_pll_clk(int pllreg)
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{
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{
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@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
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/* SDIV [2:0] */
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/* SDIV [2:0] */
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s = r & 0x7;
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s = r & 0x7;
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freq = CONFIG_SYS_CLK_FREQ_C210;
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freq = CONFIG_SYS_CLK_FREQ;
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if (pllreg == EPLL) {
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if (pllreg == EPLL) {
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k = k & 0xffff;
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k = k & 0xffff;
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@ -49,6 +49,7 @@
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/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
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/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
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#define CONFIG_SYS_CLK_FREQ_C210 24000000
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#define CONFIG_SYS_CLK_FREQ_C210 24000000
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#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_TAG
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@ -49,6 +49,7 @@
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/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
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/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
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#define CONFIG_SYS_CLK_FREQ_C210 24000000
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#define CONFIG_SYS_CLK_FREQ_C210 24000000
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#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_TAG
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