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Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro 

CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4)
architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ
to make it generic for exynos architecture.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Chander Kashyap 2012-02-05 23:01:45 +00:00 committed by Albert ARIBAUD
parent 8aca4d6436
commit 5e46f83cc3
3 changed files with 3 additions and 5 deletions
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6
arch/arm/cpu/armv7/exynos/clock.c
View File

@ -26,10 +26,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#ifndef CONFIG_SYS_CLK_FREQ_C210
#define CONFIG_SYS_CLK_FREQ_C210 24000000
#endif
/* exynos4: return pll clock frequency */
static unsigned long exynos4_get_pll_clk(int pllreg)
{
@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
/* SDIV [2:0] */
s = r & 0x7;
freq = CONFIG_SYS_CLK_FREQ_C210;
freq = CONFIG_SYS_CLK_FREQ;
if (pllreg == EPLL) {
k = k & 0xffff;

1
include/configs/s5pc210_universal.h
View File

@ -49,6 +49,7 @@
/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210 24000000
#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG

1
include/configs/trats.h
View File

@ -49,6 +49,7 @@
/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210 24000000
#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG