powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()

Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq().  If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-01-31 20:36:02 -06:00
parent 00203c6464
commit 5df4b0ad0d
29 changed files with 9 additions and 150 deletions
arch/powerpc/cpu/mpc8xxx/ddr
board
freescale
corenet_ds
mpc8536ds
mpc8540ads
mpc8541cds
mpc8544ds
mpc8548cds
mpc8555cds
mpc8560ads
mpc8568mds
mpc8569mds
mpc8572ds
mpc8610hpcd
mpc8641hpcn
p1022ds
p2020ds
sbc8548
sbc8560
sbc8641d
socrates
stx
stxgp3
stxssa
xes
xpedite517x
xpedite520x
xpedite537x
xpedite550x
include

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@ -236,7 +236,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
* tAXPD=1, need design to confirm. * tAXPD=1, need design to confirm.
*/ */
int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
unsigned int data_rate = fsl_ddr_get_mem_data_rate(); unsigned int data_rate = get_ddr_freq(0);
tmrd_mclk = 4; tmrd_mclk = 4;
/* set the turnaround time */ /* set the turnaround time */
trwt_mclk = 1; trwt_mclk = 1;

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@ -80,5 +80,4 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int mclk_to_picos(unsigned int mclk);
extern unsigned int get_memory_clk_period_ps(void); extern unsigned int get_memory_clk_period_ps(void);
extern unsigned int picos_to_mclk(unsigned int picos); extern unsigned int picos_to_mclk(unsigned int picos);
extern unsigned int fsl_ddr_get_mem_data_rate(void);
#endif #endif

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@ -11,8 +11,6 @@
#include "ddr.h" #include "ddr.h"
unsigned int fsl_ddr_get_mem_data_rate(void);
/* /*
* Round mclk_ps to nearest 10 ps in memory controller code. * Round mclk_ps to nearest 10 ps in memory controller code.
* *
@ -24,7 +22,7 @@ unsigned int get_memory_clk_period_ps(void)
{ {
unsigned int mclk_ps; unsigned int mclk_ps;
mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate(); mclk_ps = 2000000000000ULL / get_ddr_freq(0);
/* round to nearest 10 ps */ /* round to nearest 10 ps */
return 10 * ((mclk_ps + 5) / 10); return 10 * ((mclk_ps + 5) / 10);
} }
@ -40,7 +38,7 @@ unsigned int picos_to_mclk(unsigned int picos)
if (!picos) if (!picos)
return 0; return 0;
clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos; clks = get_ddr_freq(0) * (unsigned long long) picos;
clks_temp = clks; clks_temp = clks;
clks = clks / ULL_2e12; clks = clks / ULL_2e12;
if (clks_temp % ULL_2e12) { if (clks_temp % ULL_2e12) {

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@ -118,11 +118,6 @@ static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
} }
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -17,11 +17,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
} }
unsigned int
fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void void
fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)

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@ -18,11 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,11 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
} }
unsigned int
fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void void
fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)

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@ -18,12 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,12 +18,6 @@ get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -17,11 +17,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_bus_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_bus_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {
@ -144,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
/* Get clk_adjust, cpo, write_data_delay, according to the board ddr /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table. * freqency and n_banks specified in board_specific_parameters table.
*/ */
ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000; ddr_freq = get_ddr_freq(0) / 1000000;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
if (pdimm[j].n_ranks > 0) { if (pdimm[j].n_ranks > 0) {
for (i = 0; i < num_params; i++) { for (i = 0; i < num_params; i++) {

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@ -15,11 +15,6 @@
#include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h> #include <asm/fsl_ddr_dimm_params.h>
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
{ {
int ret; int ret;

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@ -17,11 +17,6 @@ static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
} }
unsigned int
fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void void
fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)

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@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_bus_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
} }
unsigned int
fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void void
fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)

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@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
} }
unsigned int
fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void void
fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)

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@ -32,11 +32,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
sizeof(ddr2_spd_eeprom_t)); sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_bus_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {
@ -144,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
unsigned int datarate; unsigned int datarate;
get_sys_info(&sysinfo); get_sys_info(&sysinfo);
datarate = fsl_ddr_get_mem_data_rate() / 1000000; datarate = get_ddr_freq(0) / 1000000;
for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
if ((bopts[i].datarate_mhz_low <= datarate) && if ((bopts[i].datarate_mhz_low <= datarate) &&

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@ -27,11 +27,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
} }
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -33,11 +33,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
sizeof(ddr2_spd_eeprom_t)); sizeof(ddr2_spd_eeprom_t));
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num) unsigned int ctrl_num)
{ {

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@ -46,11 +46,6 @@ void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
} }
} }
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
/* /*
* There are traditionally three board-specific SDRAM timing parameters * There are traditionally three board-specific SDRAM timing parameters
* which must be calculated based on the particular PCB artwork. These are: * which must be calculated based on the particular PCB artwork. These are:

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@ -538,6 +538,10 @@ ulong get_ddr_freq (ulong);
#if defined(CONFIG_MPC86xx) #if defined(CONFIG_MPC86xx)
typedef MPC86xx_SYS_INFO sys_info_t; typedef MPC86xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * ); void get_sys_info ( sys_info_t * );
static inline ulong get_ddr_freq(ulong dummy)
{
return get_bus_freq(dummy);
}
#endif #endif
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) #if defined(CONFIG_4xx) || defined(CONFIG_IOP480)