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Cleanup whitespaces and style issues. 

Removed //-style comments.
Use 80-column lines.
Remove trailing whitespace.
Remove dead code and debug cruft.
This commit is contained in:
Jon Loeliger 2006-04-27 10:15:16 -05:00
parent a2320a6bf8
commit 5c9efb36a6
13 changed files with 434 additions and 550 deletions

33
board/mpc8641hpcn/mpc8641hpcn.c
View File

@ -57,9 +57,6 @@ int checkboard (void)
#ifdef CONFIG_PCI
/* Sri: Note that at this point we will only test on PCI1
*/
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile ccsr_pex_t *pex1 = &immap->im_pex1;
@ -70,13 +67,16 @@ int checkboard (void)
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
debug ("PCI-EXPRESS 1: %s \n",
pex1_agent ? "Agent" : "Host");
if ((io_sel==2 || io_sel==3 || io_sel==5 \
|| io_sel==6 || io_sel==7 || io_sel==0xF)
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
debug ("PCI-EXPRESS 1: %s \n",
pex1_agent ? "Agent" : "Host");
debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
if (pex1->pme_msg_det) {
pex1->pme_msg_det = 0xffffffff;
debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det);
debug (" with errors. Clearing. Now 0x%08x",
pex1->pme_msg_det);
}
debug ("\n");
} else {
@ -120,15 +120,6 @@ initdram(int board_type)
ddr_enable_ecc(dram_size);
#endif
/*
* Initialize SDRAM. Currently HPCN doesn't have
* SDRAM but we'll leave this here for now
* in case someone changes their mind
*/
#if !defined(CONFIG_MPC8641HPCN)
// sdram_init();
#endif
puts(" DDR: ");
return dram_size;
}
@ -163,7 +154,7 @@ local_bus_init(void)
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
int testdram(void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
@ -198,10 +189,10 @@ int testdram (void)
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
long int fixed_sdram(void)
{
#if !defined(CFG_RAMBOOT)
volatile immap_t *immap = (immap_t *)CFG_IMMR;

2
board/mpc8641hpcn/oftree.dts
View File

@ -1,5 +1,5 @@
/*
* MPC8641 HPCn Device Tree Source
* MPC8641 HPCN Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*

258
cpu/mpc86xx/cpu.c
View File

@ -32,31 +32,30 @@
#include <ft_build.h>
#endif
extern unsigned long get_board_sys_clk(ulong dummy);
// SS: For debug only, remove after use
static __inline__ unsigned long get_dbat3u (void)
{
unsigned long dbat3u;
asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
return dbat3u;
unsigned long dbat3u;
asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
return dbat3u;
}
static __inline__ unsigned long get_dbat3l (void)
{
unsigned long dbat3l;
asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
return dbat3l;
unsigned long dbat3l;
asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
return dbat3l;
}
static __inline__ unsigned long get_msr (void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr;
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr;
}
extern unsigned long get_board_sys_clk(ulong dummy);
int checkcpu (void)
{
@ -66,7 +65,7 @@ int checkcpu (void)
uint major, minor;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
puts("Freescale PowerPC\n");
pvr = get_pvr();
@ -74,10 +73,10 @@ int checkcpu (void)
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
puts ("CPU:\n");
puts("CPU:\n");
printf(" Core: ");
switch (ver) {
case PVR_VER(PVR_86xx):
puts("E600");
@ -94,7 +93,7 @@ int checkcpu (void)
minor = SVR_MIN(svr);
puts(" System: ");
switch (ver) {
switch (ver) {
case SVR_8641:
puts("8641");
break;
@ -113,7 +112,7 @@ int checkcpu (void)
printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
#if defined(CFG_LBC_LCRR)
lcrr = CFG_LBC_LCRR;
#else
@ -134,11 +133,11 @@ int checkcpu (void)
printf(" L2: ");
if (get_l2cr() & 0x80000000)
printf("Enabled\n");
printf("Enabled\n");
else
printf("Disabled\n");
return (0);
printf("Disabled\n");
return 0;
}
@ -149,7 +148,7 @@ soft_restart(unsigned long addr)
{
#ifndef CONFIG_MPC8641HPCN
/* SRR0 has system reset vector, SRR1 has default MSR value */
/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
@ -215,7 +214,7 @@ int set_px_sysclk(ulong sysclk)
sysclk_s = 0x06;
sysclk_r = 0x1F;
sysclk_v = 0x3B;
sysclk_aux = 0x06;
sysclk_aux = 0x06;
break;
case 166:
sysclk_s = 0x06;
@ -227,14 +226,14 @@ int set_px_sysclk(ulong sysclk)
printf("Unsupported SYSCLK frequency.\n");
return 0;
}
vclkh = (sysclk_s << 5) | sysclk_r ;
vclkl = sysclk_v;
out8(PIXIS_BASE+PIXIS_VCLKH,vclkh);
out8(PIXIS_BASE+PIXIS_VCLKL,vclkl);
out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux);
return 1;
}
@ -262,7 +261,7 @@ int set_px_mpxpll(ulong mpxpll)
tmp = in8(PIXIS_BASE+PIXIS_VSPEED1);
tmp = (tmp & 0xF0) | (val & 0x0F);
out8(PIXIS_BASE+PIXIS_VSPEED1,tmp);
return 1;
}
@ -270,9 +269,8 @@ int set_px_corepll(ulong corepll)
{
u8 tmp;
u8 val;
switch((int)corepll)
{
switch ((int)corepll) {
case 20:
val = 0x08;
break;
@ -295,11 +293,11 @@ int set_px_corepll(ulong corepll)
printf("Unsupported COREPLL ratio.\n");
return 0;
}
tmp = in8(PIXIS_BASE+PIXIS_VSPEED0);
tmp = (tmp & 0xE0) | (val & 0x1F);
out8(PIXIS_BASE+PIXIS_VSPEED0,tmp);
return 1;
}
@ -311,7 +309,7 @@ void read_from_px_regs(int set)
tmp = tmp | mask;
else
tmp = tmp & ~mask;
out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
}
void read_from_px_regs_altbank(int set)
@ -322,7 +320,7 @@ void read_from_px_regs_altbank(int set)
tmp = tmp | mask;
else
tmp = tmp & ~mask;
out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
}
void set_altbank(void)
@ -342,7 +340,7 @@ void set_px_go(void)
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
tmp = tmp | 0x01;
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
}
void set_px_go_with_watchdog(void)
@ -353,7 +351,7 @@ void set_px_go_with_watchdog(void)
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
tmp = tmp | 0x09;
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
}
/* This function takes the non-integral cpu:mpx pll ratio
@ -381,11 +379,11 @@ ulong strfractoint(uchar *strptr)
no_dec = 1;
break; /* Break from loop once the end of string is reached */
}
intarr[i] = strptr[i];
i++;
}
intarr_len = i; /* Assign length of integer part to intarr_len*/
intarr[i] = '\0'; /* */
@ -404,14 +402,14 @@ ulong strfractoint(uchar *strptr)
i++;
j++;
}
decarr_len = j;
decarr[j] = '\0';
mulconst=1;
for(i=0; i<decarr_len;i++)
mulconst = mulconst*10;
decval = simple_strtoul(decarr,NULL,10);
decval = simple_strtoul(decarr,NULL,10);
}
intval = simple_strtoul(intarr,NULL,10);
@ -422,9 +420,9 @@ ulong strfractoint(uchar *strptr)
return retval;
}
#endif //CONFIG_MPC8641HPCN
#endif /* CONFIG_MPC8641HPCN */
/* no generic way to do board reset. simply call soft_reset. */
@ -434,8 +432,6 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char cmd;
ulong addr, val;
ulong corepll;
#ifdef CFG_RESET_ADDRESS
addr = CFG_RESET_ADDRESS;
@ -451,7 +447,7 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#ifndef CONFIG_MPC8641HPCN
/* flush and disable I/D cache */
/* flush and disable I/D cache */
__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
@ -467,97 +463,85 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
soft_restart(addr);
#else /* CONFIG_MPC8641HPCN */
if(argc > 1)
{
cmd = argv[1][1];
switch(cmd)
{
case 'f': /* reset with frequency changed */
if (argc < 5)
goto my_usage;
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10));
if(val == 3)
{
printf("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
set_px_go();
}
else
goto my_usage;
while(1); /* Not reached */
case 'l':
if(argv[2][1] == 'f')
{
read_from_px_regs(0);
read_from_px_regs_altbank(0);
/* reset with frequency changed */
val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
corepll = strfractoint(argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
if(val == 3)
{
printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
set_px_go_with_watchdog();
}
else
goto my_usage;
while(1); /* Not reached */
}
else /* Reset from next bank without changing frequencies */
{
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if(argc > 2)
goto my_usage;
printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog();
while(1); /* Not reached */
}
if (argc > 1) {
cmd = argv[1][1];
switch(cmd) {
case 'f': /* reset with frequency changed */
if (argc < 5)
goto my_usage;
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4],
NULL, 10));
if (val == 3) {
printf("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
set_px_go();
} else
goto my_usage;
while (1); /* Not reached */
case 'l':
if (argv[2][1] == 'f') {
read_from_px_regs(0);
read_from_px_regs_altbank(0);
/* reset with frequency changed */
val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
corepll = strfractoint(argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
if (val == 3) {
printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
set_px_go_with_watchdog();
} else
goto my_usage;
while(1); /* Not reached */
} else {
/* Reset from next bank without changing frequencies */
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if(argc > 2)
goto my_usage;
printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog();
while(1); /* Not reached */
}
default:
goto my_usage;
}
default:
goto my_usage;
}
my_usage:
printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
printf("For example: reset cf 40 2.5 10\n");
printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
return;
}
else
out8(PIXIS_BASE+PIXIS_RST,0);
printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
printf("For example: reset cf 40 2.5 10\n");
printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
return;
} else
out8(PIXIS_BASE+PIXIS_RST,0);
#endif /* !CONFIG_MPC8641HPCN */
while(1); /* not reached */
}
/* ------------------------------------------------------------------------- */
/*
* Get timebase clock frequency
*/
@ -566,24 +550,21 @@ unsigned long get_tbclk(void)
sys_info_t sys_info;
get_sys_info(&sys_info);
return ((sys_info.freqSystemBus + 3L) / 4L);
return (sys_info.freqSystemBus + 3L) / 4L;
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
}
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
void dma_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
@ -593,7 +574,8 @@ void dma_init(void) {
return;
}
uint dma_check(void) {
uint dma_check(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
volatile uint status = dma->sr0;
@ -609,7 +591,8 @@ uint dma_check(void) {
return status;
}
int dma_xfer(void *dest, uint count, void *src) {
int dma_xfer(void *dest, uint count, void *src)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
@ -622,6 +605,7 @@ int dma_xfer(void *dest, uint count, void *src) {
asm("sync;isync");
return dma_check();
}
#endif /* CONFIG_DDR_ECC */
@ -631,7 +615,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
u32 *p;
ulong clock;
int len;
clock = bd->bi_busfreq;
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
@ -649,7 +633,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
memcpy(p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
memcpy(p, bd->bi_enet1addr, 6);

17
cpu/mpc86xx/cpu_init.c
View File

@ -36,13 +36,12 @@
* initialize a bunch of registers
*/
void cpu_init_f (void)
void cpu_init_f(void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
//u8 val;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
@ -72,23 +71,21 @@ void cpu_init_f (void)
memctl->br1 = CFG_BR1_PRELIM;
#endif
//#if !defined(CONFIG_MPC86xx)
#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
memctl->or2 = CFG_OR2_PRELIM;
memctl->br2 = CFG_BR2_PRELIM;
#endif
//#endif
#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
memctl->or3 = CFG_OR3_PRELIM;
memctl->br3 = CFG_BR3_PRELIM;
#endif
#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
memctl->or4 = CFG_OR4_PRELIM;
memctl->br4 = CFG_BR4_PRELIM;
#endif
#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
memctl->or5 = CFG_OR5_PRELIM;
memctl->br5 = CFG_BR5_PRELIM;
@ -123,9 +120,9 @@ void cpu_init_f (void)
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r (void)
int cpu_init_r(void)
{
return (0);
return 0;
}

68
cpu/mpc86xx/i2c.c
View File

@ -74,29 +74,27 @@ i2c_init(int speed, int slaveadd)
}
static __inline__ int
i2c_wait4bus (void)
i2c_wait4bus(void)
{
ulong timeval = get_timer (0);
// debug("I2C: Wait for bus\n");
while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) {
if (get_timer (timeval) > TIMEOUT) {
if (get_timer(timeval) > TIMEOUT) {
return -1;
}
}
return 0;
return 0;
}
static __inline__ int
i2c_wait (int write)
i2c_wait(int write)
{
u32 csr;
ulong timeval = get_timer (0);
do {
csr = readb(I2CCSR);
if (!(csr & MPC86xx_I2CSR_MIF))
continue;
@ -118,7 +116,7 @@ i2c_wait (int write)
}
return 0;
} while (get_timer (timeval) < TIMEOUT);
} while (get_timer(timeval) < TIMEOUT);
debug("i2c_wait: timed out\n");
return -1;
@ -127,14 +125,13 @@ i2c_wait (int write)
static __inline__ int
i2c_write_addr (u8 dev, u8 dir, int rsta)
{
// debug("I2C: Write Addr\n");
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX |
(rsta?MPC86xx_I2CCR_RSTA:0),
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX
| (rsta ? MPC86xx_I2CCR_RSTA : 0),
I2CCCR);
writeb((dev << 1) | dir, I2CCDR);
if (i2c_wait (I2C_WRITE) < 0)
if (i2c_wait(I2C_WRITE) < 0)
return 0;
return 1;
@ -144,14 +141,14 @@ static __inline__ int
__i2c_write (u8 *data, int length)
{
int i;
// debug("I2C: __i2c_write\n");
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX,
I2CCCR);
for (i=0; i < length; i++) {
for (i = 0; i < length; i++) {
writeb(data[i], I2CCDR);
if (i2c_wait (I2C_WRITE) < 0)
if (i2c_wait(I2C_WRITE) < 0)
break;
}
@ -163,33 +160,30 @@ __i2c_read (u8 *data, int length)
{
int i;
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA |
((length == 1) ? MPC86xx_I2CCR_TXAK : 0),
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA
| ((length == 1) ? MPC86xx_I2CCR_TXAK : 0),
I2CCCR);
/* dummy read */
readb(I2CCDR);
// debug("length = %d\n", length);
for (i=0; i < length; i++) {
if (i2c_wait (I2C_READ) < 0)
for (i = 0; i < length; i++) {
if (i2c_wait(I2C_READ) < 0)
break;
/* Generate ack on last next to last byte */
if (i == length - 2)
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA |
MPC86xx_I2CCR_TXAK,
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA
| MPC86xx_I2CCR_TXAK,
I2CCCR);
/* Generate stop on last byte */
if (i == length - 1)
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR);
// debug("I2CCR = 0x%08x\n", readb(I2CCCR));
data[i] = readb(I2CCDR);
// debug("data[i] = 0x%08x\n", data[i]);
}
// debug("Returning i = %d\n", i);
return i;
}
@ -199,19 +193,19 @@ i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
int i = 0;
u8 *a = (u8*)&addr;
if (i2c_wait4bus () < 0)
if (i2c_wait4bus() < 0)
goto exit;
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
if (i2c_write_addr(dev, I2C_WRITE, 0) == 0)
goto exit;
if (__i2c_write (&a[4 - alen], alen) != alen)
if (__i2c_write(&a[4 - alen], alen) != alen)
goto exit;
if (i2c_write_addr (dev, I2C_READ, 1) == 0)
if (i2c_write_addr(dev, I2C_READ, 1) == 0)
goto exit;
i = __i2c_read (data, length);
i = __i2c_read(data, length);
exit:
writeb(MPC86xx_I2CCR_MEN, I2CCCR);
@ -225,16 +219,16 @@ i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
int i = 0;
u8 *a = (u8*)&addr;
if (i2c_wait4bus () < 0)
if (i2c_wait4bus() < 0)
goto exit;
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
if (i2c_write_addr(dev, I2C_WRITE, 0) == 0)
goto exit;
if (__i2c_write (&a[4 - alen], alen) != alen)
if (__i2c_write(&a[4 - alen], alen) != alen)
goto exit;
i = __i2c_write (data, length);
i = __i2c_write(data, length);
exit:
writeb(MPC86xx_I2CCR_MEN, I2CCCR);
@ -253,21 +247,21 @@ int i2c_probe (uchar chip)
*/
udelay(10000);
return i2c_read (chip, 0, 1, (char *)&tmp, 1);
return i2c_read(chip, 0, 1, (char *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
char buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
i2c_read(i2c_addr, reg, 1, buf, 1);
return (buf[0]);
return buf[0];
}
void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
{
i2c_write (i2c_addr, reg, 1, &val, 1);
i2c_write(i2c_addr, reg, 1, &val, 1);
}
#endif /* CONFIG_HARD_I2C */

23
cpu/mpc86xx/interrupts.c
View File

@ -75,7 +75,7 @@ static __inline__ void set_dec (unsigned long val)
/* interrupt is not supported yet */
int interrupt_init_cpu (unsigned *decrementer_count)
{
return (0);
return 0;
}
@ -91,14 +91,14 @@ int interrupt_init (void)
decrementer_count = get_tbclk()/CFG_HZ;
debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count);
set_dec (decrementer_count);
set_msr (get_msr () | MSR_EE);
debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec());
return (0);
return 0;
}
@ -113,7 +113,7 @@ int disable_interrupts (void)
ulong msr = get_msr ();
set_msr (msr & ~MSR_EE);
return ((msr & MSR_EE) != 0);
return (msr & MSR_EE) != 0;
}
@ -131,7 +131,6 @@ void
timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
}
@ -139,14 +138,14 @@ void timer_interrupt (struct pt_regs *regs)
{
/* call cpu specific function from $(CPU)/interrupts.c */
timer_interrupt_cpu (regs);
timestamp++;
ppcDcbf(&timestamp);
/* Restore Decrementer Count */
set_dec (decrementer_count);
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0)
WATCHDOG_RESET ();
@ -169,8 +168,8 @@ void reset_timer (void)
}
ulong get_timer (ulong base)
{
return (timestamp - base);
{
return timestamp - base;
}
void set_timer (ulong t)
@ -185,13 +184,11 @@ void set_timer (ulong t)
void
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
return;
}
void
irq_free_handler(int vec)
{
return;
}

105
cpu/mpc86xx/pci.c
View File

@ -22,7 +22,7 @@
*/
/*
* PEX Configuration space access support for MPC85xx PEX Bridge
* PEX Configuration space access support for PEX Bridge
*/
#include <common.h>
#include <pci.h>
@ -44,24 +44,25 @@ pci_mpc86xx_init(struct pci_controller *hose)
ulong addr, data;
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
if ((io_sel==2 || io_sel==3 || io_sel==5
|| io_sel==6 || io_sel==7 || io_sel==0xF )
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
printf ("PCI-EXPRESS 1: Configured as %s \n",
pex1_agent ? "Agent" : "Host");
printf (" Scanning PCI bus");
debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
if (pex1->pme_msg_det) {
pex1->pme_msg_det = 0xffffffff;
debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det);
debug (" with errors. Clearing. Now 0x%08x",
pex1->pme_msg_det);
}
debug ("\n");
}
hose->first_busno = 0;
hose->last_busno = 0x7f;
@ -88,36 +89,26 @@ pci_mpc86xx_init(struct pci_controller *hose)
*/
pci_register_hose(hose);
//#define MPC8548_REV1_PEX12_ERRATA
#ifdef MPC8548_REV1_PEX12_ERRATA
/* can only read/write 4 bytes */
pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, &reg32);
printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32);
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg32);
reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32);
#else
pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, &reg16);
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16);
pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, &reg16);
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16);
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY \
| PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16);
#endif
/*
* Clear non-reserved bits in status register.
*/
// pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
// pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
/*
* pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
* pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
*/
pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pex1->powar1 = 0x8004401c; /* 512M MEM space */
@ -129,7 +120,6 @@ pci_mpc86xx_init(struct pci_controller *hose)
pex1->potar2 = 0x00000000;
pex1->potear2 = 0x00000000;
if (!pex1->piwar1) {
pex1->pitar1 = 0x00000000;
pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff;
@ -140,57 +130,34 @@ pci_mpc86xx_init(struct pci_controller *hose)
pex1->pitar2 = 0x00000000;
pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff;
pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
* Snoop R/W, 2G */
/* if (pex1_host) { */
/* #ifdef MPC8548_REV1_PEX12_ERRATA */
/* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */
/* #else */
*(u32 *)(0xf8008000)= 0x80000000;
debug("Received data for addr 0x%08lx is 0x%08lx\n",
*(u32*)(0xf8008000), *(u32*)(0xf8008004));
pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20);
pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00);
pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F);
*(u32 *)(0xf8008000)= 0x80200000;
debug("Received data for addr 0x%08lx is 0x%08lx\n",
*(u32*)(0xf8008000), *(u32*)(0xf8008004));
*(u32 *)(0xf8008000)= 0x80000000;
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
*(u32 *)(0xf8008000)= 0x80200000;
debug("Received data for addr 0x%08lx is 0x%08lx\n",
*(u32*)(0xf8008000), *(u32*)(0xf8008004));
*(u32 *)(0xf8008000)= 0x80200000;
debug("Received data for addr 0x%08lx is 0x%08lx\n",
*(u32*)(0xf8008000), *(u32*)(0xf8008004));
pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20);
pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00);
pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F);
/* #endif */
*(u32 *)(0xf8008000)= 0x80200000;
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
*(u32 *)(0xf8008000)= 0x80200000;
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
*(u32 *)(0xf8008000)= 0x80200000;
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
hose->last_busno = pci_hose_scan(hose);
hose->last_busno = 0x21;
debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno);
debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno);
printf("....PCI scan & enumeration done\n");
/* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */
/* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */
/* if (hose->last_busno < 1) { */
/* hose->last_busno=1; /\*Hack*\/ */
/* } else { */
/* hose->last_busno = 0; */
/* } */
/*}*/
/* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, &reg32); */
/* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */
hose->last_busno = pci_hose_scan(hose);
hose->last_busno = 0x21;
debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno);
debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno);
printf("....PCI scan & enumeration done\n");
}
#endif /* CONFIG_PCI */

9
cpu/mpc86xx/spd_sdram.c
View File

@ -179,7 +179,7 @@ spd_sdram(void)
unsigned int law_size;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
/*
* Read SPD information.
*/
@ -614,7 +614,7 @@ spd_sdram(void)
ddr1->timing_cfg_2 = (0
| ((add_lat & 0x7) << 28) /* ADD_LAT */
| ((cpo & 0x1f) << 23) /* CPO */
| ((cpo & 0x1f) << 23) /* CPO */
| ((wr_lat & 0x7) << 19) /* WR_LAT */
| ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
| ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
@ -806,7 +806,7 @@ spd_sdram(void)
/*
* Memory will be initialized via DMA, or not at all.
*/
d_init = 0;
d_init = 0;
#endif
ddr1->sdram_cfg_2 = (0
@ -946,8 +946,7 @@ spd_sdram(void)
| (LAWAR_SIZE & law_size));
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
debug("DDR: LARAR1=0x%08x\n", mcm->lawar1);
return memsize * 1024 * 1024;
}

254
cpu/mpc86xx/speed.c
View File

@ -33,9 +33,7 @@ unsigned long get_board_sys_clk(ulong dummy);
unsigned long get_sysclk_from_px_regs(void);
/* --------------------------------------------------------------- */
void get_sys_info (sys_info_t * sysInfo)
void get_sys_info (sys_info_t *sysInfo)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
@ -43,7 +41,7 @@ void get_sys_info (sys_info_t * sysInfo)
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
switch(plat_ratio) {
case 0x0:
sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
@ -65,72 +63,77 @@ void get_sys_info (sys_info_t * sysInfo)
break;
}
// printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", sysInfo->freqSystemBus, plat_ratio);
#if 0
printf("assigned system bus freq = %d for plat ratio 0x%08lx\n",
sysInfo->freqSystemBus, plat_ratio);
#endif
e600_ratio = (gur->porpllsr) & 0x003f0000;
e600_ratio >>= 16;
switch(e600_ratio) {
switch (e600_ratio) {
case 0x10:
sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
break;
case 0x19:
sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
case 0x19:
sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2;
break;
case 0x20:
sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
break;
case 0x39:
sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2;
break;
case 0x28:
sysInfo->freqProcessor = 4*sysInfo->freqSystemBus;
sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
break;
case 0x1d:
sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2;
sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2;
break;
default:
/* JB - Emulator workaround until real cop is plugged in */
sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
//sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
/* JB - Emulator workaround until real cop is plugged in */
/* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */
sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
break;
}
// printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", sysInfo->freqProcessor, e600_ratio);
#if 0
printf("assigned processor freq = %d for e600 ratio 0x%08lx\n",
sysInfo->freqProcessor, e600_ratio);
#endif
}
/* ------------------------------------------------------------------------- */
/*
* Measure CPU clock speed (core clock GCLK1, GCLK2)
*
* (Approx. GCLK frequency in Hz)
*/
int get_clocks (void)
int get_clocks(void)
{
DECLARE_GLOBAL_DATA_PTR;
sys_info_t sys_info;
get_sys_info (&sys_info);
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
if(gd->cpu_clk != 0) return (0);
else return (1);
if (gd->cpu_clk != 0)
return 0;
else
return 1;
}
/* ------------------------------------------------------------------------- */
/********************************************
/*
* get_bus_freq
* return system bus freq in Hz
*********************************************/
ulong get_bus_freq (ulong dummy)
* Return system bus freq in Hz
*/
ulong get_bus_freq(ulong dummy)
{
ulong val;
sys_info_t sys_info;
get_sys_info (&sys_info);
get_sys_info(&sys_info);
val = sys_info.freqSystemBus;
return val;
@ -138,111 +141,100 @@ ulong get_bus_freq (ulong dummy)
unsigned long get_sysclk_from_px_regs()
{
ulong val;
u8 vclkh,vclkl;
vclkh = in8(PIXIS_BASE+PIXIS_VCLKH);
vclkl = in8(PIXIS_BASE+PIXIS_VCLKL);
if((vclkh == 0x84) && (vclkl ==0x07))
{
val = 33000000;
}
if((vclkh == 0x3F) && (vclkl ==0x20))
{
val = 40000000;
}
if((vclkh == 0x3F) && (vclkl ==0x2A))
{
val = 50000000;
}
if((vclkh == 0x24) && (vclkl ==0x04))
{
val = 66000000;
}
if((vclkh == 0x3F) && (vclkl ==0x4B))
{
val = 83000000;
}
if((vclkh == 0x3F) && (vclkl ==0x5C))
{
val = 100000000;
}
if((vclkh == 0xDF) && (vclkl ==0x3B))
{
val = 134000000;
}
if((vclkh == 0xDF) && (vclkl ==0x4B))
{
val = 166000000;
}
return val;
ulong val;
u8 vclkh, vclkl;
vclkh = in8(PIXIS_BASE + PIXIS_VCLKH);
vclkl = in8(PIXIS_BASE + PIXIS_VCLKL);
if ((vclkh == 0x84) && (vclkl == 0x07)) {
val = 33000000;
}
if ((vclkh == 0x3F) && (vclkl == 0x20)) {
val = 40000000;
}
if ((vclkh == 0x3F) && (vclkl == 0x2A)) {
val = 50000000;
}
if ((vclkh == 0x24) && (vclkl == 0x04)) {
val = 66000000;
}
if ((vclkh == 0x3F) && (vclkl == 0x4B)) {
val = 83000000;
}
if ((vclkh == 0x3F) && (vclkl == 0x5C)) {
val = 100000000;
}
if ((vclkh == 0xDF) && (vclkl == 0x3B)) {
val = 134000000;
}
if ((vclkh == 0xDF) && (vclkl == 0x4B)) {
val = 166000000;
}
return val;
}
/******* From MPC8641HPCN Design Workbook ************
*
/*
* get_board_sys_clk
* reads the FPGA on board for CONFIG_SYS_CLK_FREQ
*
********************************************************/
* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
*/
unsigned long get_board_sys_clk(ulong dummy)
{
u8 i, go_bit, rd_clks;
ulong val;
u8 i, go_bit, rd_clks;
ulong val;
go_bit = in8(PIXIS_BASE+PIXIS_VCTL);
go_bit &= 0x01;
go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
go_bit &= 0x01;
rd_clks = in8(PIXIS_BASE+PIXIS_VCFGEN0);
rd_clks &= 0x1C;
rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
rd_clks &= 0x1C;
/* Only if both go bit and the SCLK bit in VCFGEN0 are set
* should we be using the AUX register. Remember, we also set the
* GO bit to boot from the alternate bank on the on-board flash
*/
if(go_bit)
{
if(rd_clks == 0x1c)
i = in8(PIXIS_BASE+PIXIS_AUX);
else
i = in8(PIXIS_BASE+PIXIS_SPD);
//val = get_sysclk_from_px_regs();
}
else
i = in8(PIXIS_BASE+PIXIS_SPD);
i &= 0x07;
switch(i)
{
case 0:
val = 33000000;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66000000;
break;
case 4:
val = 83000000;
break;
case 5:
val = 100000000;
break;
case 6:
val = 134000000;
break;
case 7:
val = 166000000;
break;
}
return val;
/*
* Only if both go bit and the SCLK bit in VCFGEN0 are set
* should we be using the AUX register. Remember, we also set the
* GO bit to boot from the alternate bank on the on-board flash
*/
if (go_bit) {
if (rd_clks == 0x1c)
i = in8(PIXIS_BASE + PIXIS_AUX);
else
i = in8(PIXIS_BASE + PIXIS_SPD);
} else {
i = in8(PIXIS_BASE + PIXIS_SPD);
}
i &= 0x07;
switch (i) {
case 0:
val = 33000000;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66000000;
break;
case 4:
val = 83000000;
break;
case 5:
val = 100000000;
break;
case 6:
val = 134000000;
break;
case 7:
val = 166000000;
break;
}
return val;
}

4
cpu/mpc86xx/start.S
View File

@ -783,12 +783,12 @@ ppcDcbz:
dcbz r0,r3
blr
/*------------------------------------------------------------------------------- */
/*-------------------------------------------------------------------------- */
/* Function: ppcSync */
/* Description: Processor Synchronize */
/* Input: none. */
/* Output: none. */
/*------------------------------------------------------------------------------- */
/*-------------------------------------------------------------------------- */
.globl ppcSync
ppcSync:
sync

2
cpu/mpc86xx/traps.c
View File

@ -1,6 +1,4 @@
/*
* linux/arch/ppc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Modified by Cort Dougan (cort@cs.nmt.edu)

203
include/configs/MPC8641HPCN.h
View File

@ -1,5 +1,6 @@
/*
* Copyright 2004 Freescale Semiconductor.
/*
* Copyright 2006 Freescale Semiconductor.
*
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@ -22,8 +23,7 @@
*/
/*
* mpc8641hpc3 board configuration file
*
* MPC8641HPCN board configuration file
*
* Make sure you change the MAC address and other network params first,
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
@ -38,48 +38,38 @@
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#undef DEBUG
#undef DEBUG
//#define RUN_DIAG 1
#ifdef RUN_DIAG
#define CFG_DIAG_ADDR 0xff800000
#endif
#define CFG_RESET_ADDRESS 0xfff00100
//#define CONFIG_PCI
#undef CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */
/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_ALTIVEC 1
#define CONFIG_ALTIVEC 1
/*-----------------------------------------------------------------------
/*
* L2CR setup -- make sure this is right for your board!
*/
#define CFG_L2
#define CFG_L2
#define L2_INIT 0
#define L2_ENABLE (L2CR_L2E)
#ifndef CONFIG_SYS_CLK_FREQ
//#define CONFIG_SYS_CLK_FREQ 33000000
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
/* JB - XXX - Are these available on 86xx? */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
@ -130,10 +120,10 @@
#define CFG_DDR_INTERVAL 0x06090100
#define CFG_DDR_DATA_INIT 0xdeadbeef
#define CFG_DDR_CLK_CTRL 0x03800000
#define CFG_DDR_OCD_CTRL 0x00000000
#define CFG_DDR_OCD_STATUS 0x00000000
#define CFG_DDR_OCD_CTRL 0x00000000
#define CFG_DDR_OCD_STATUS 0x00000000
#define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
#define CFG_DDR_CONTROL2 0x04400000
#define CFG_DDR_CONTROL2 0x04400000
//Not used in fixed_sdram function
@ -143,20 +133,12 @@
#define CFG_DDR_CS3_BNDS 0x00000FFF //Not done
#define CFG_DDR_CS4_BNDS 0x00000FFF //Not done
#define CFG_DDR_CS5_BNDS 0x00000FFF //Not done
#endif
#endif
/*
* SDRAM on the Local Bus
*/
//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
* We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
* map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
* However, when u-boot comes up, the flash_init needs hard start addresses
@ -165,15 +147,12 @@
* knows where the flash is and the user can download u-boot code from promjet to
* fef00000 <- more intuitive than fe700000. Note that, on switching the boot
* location, fef00000 becomes fff00000.
*/
*/
#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
#define CFG_FLASH_BASE2 0xff800000
#define CFG_FLASH_BASE2 0xff800000
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
/*Sri: This looks like a good place to init all the Local Bus chip selects*/
#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */
#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
@ -186,25 +165,24 @@
#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/
#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/
#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/
#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/
#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
#define PIXIS_VCTL 0x10 /* VELA Control Register */
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
#define PIXIS_VCTL 0x10 /* VELA Control Register */
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
@ -212,11 +190,9 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
/*#define CFG_HPCN_FLASH_CFI_DRIVER */
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
@ -230,7 +206,7 @@
#undef CONFIG_CLOCKS_IN_MHZ
#define CONFIG_L1_INIT_RAM
#undef CFG_INIT_RAM_LOCK
#undef CFG_INIT_RAM_LOCK
#ifndef CFG_INIT_RAM_LOCK
#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
#else
@ -265,20 +241,22 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/*
* Pass open firmware flat tree to kernel
*/
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8641@0"
#define OF_SOC "soc8641@f8000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500"
#define OF_CPU "PowerPC,8641@0"
#define OF_SOC "soc8641@f8000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500"
#define CFG_64BIT_VSPRINTF 1
#define CFG_64BIT_STRTOUL 1
#define CFG_64BIT_VSPRINTF 1
#define CFG_64BIT_STRTOUL 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
@ -297,13 +275,10 @@
* Addresses are mapped 1-1.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
//#define CFG_PCI1_MEM_BASE 0xd0000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
//#define CFG_PCI1_IO_BASE 0xe0000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
//#define CFG_PCI1_IO_BUS 0x00000000
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
/* For RTL8139 */
@ -316,29 +291,18 @@
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
// #define CFG_PCI1_MEM_BASE 0x80000000
// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
// #define CFG_PCI1_IO_BASE 0xe2000000
// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
//#define CFG_SCSI_SCAN_BUS_REVERSE
#undef CFG_SCSI_SCAN_BUS_REVERSE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_RTL8139
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@ -349,7 +313,6 @@
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
@ -371,7 +334,6 @@
#define CONFIG_MPC86XX_TSEC4 1
#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
@ -389,12 +351,10 @@
/* BAT0 2G Cacheable, non-guarded
* 0x0000_0000 2G DDR
*/
//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE)
#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP)
//#define CFG_IBAT0L CFG_DBAT0L
//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP )
#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
#define CFG_IBAT0U CFG_DBAT0U
/* BAT1 1G Cache-inhibited, guarded
@ -402,7 +362,8 @@
* 0xa000_0000 512M PCI-Express 2 Memory
** SS - Changed it for operating from 0xd0000000
*/
#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U CFG_DBAT1U
@ -410,7 +371,8 @@
/* BAT2 512M Cache-inhibited, guarded
* 0xc000_0000 512M RapidIO Memory
*/
#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U CFG_DBAT2U
@ -418,7 +380,8 @@
/* BAT3 4M Cache-inhibited, guarded
* 0xf800_0000 4M CCSR
*/
#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U CFG_DBAT3U
@ -428,7 +391,8 @@
* 0xe300_0000 16M PCI-Express 2 I/0
** SS - Note that this is at 0xe0000000
*/
#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT4U CFG_DBAT4U
@ -444,12 +408,12 @@
/* BAT6 32M Cache-inhibited, guarded
* 0xfe00_0000 32M FLASH
*/
#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CFG_IBAT6U CFG_DBAT6U
#define CFG_DBAT7L 0x00000000
#define CFG_DBAT7U 0x00000000
#define CFG_IBAT7L 0x00000000
@ -461,17 +425,17 @@
/*
* Environment
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@ -572,24 +536,25 @@
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
#define CONFIG_HAS_ETH3 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
#define CONFIG_HAS_ETH3 1
#define CONFIG_IPADDR 10.82.193.138
#define CONFIG_IPADDR 10.82.193.138
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /opt/nfsroot
#define CONFIG_BOOTFILE uImage
#define CONFIG_SERVERIP 10.82.193.104
#define CONFIG_GATEWAYIP 10.82.193.254
#define CONFIG_NETMASK 255.255.252.0
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 10.82.193.104
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
#define CONFIG_BAUDRATE 115200
@ -599,7 +564,7 @@
"consoledev=ttyS0\0" \
"ramdiskaddr=400000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
"pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \
"pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\
"pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
"pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
"pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \

6
include/mpc86xx.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright 2006 Freescale Semiconductor.
* Jeffrey Brown (jeffrey@freescale.com)
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*/
@ -9,7 +9,7 @@
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
/*----------------------------------------------------------------
/*
* l2cr values. Look in config_<BOARD>.h for the actual setup
*/
#define l2cr 1017
@ -23,7 +23,7 @@
#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
/*----------------------------------------------------------------
/*
* BAT settings. Look in config_<BOARD>.h for the actual setup
*/