arm: ls102xa: enable snooping for CAAM transactions
Enable snooping for CAAM read & write transactions by programming the SCFG snoop configuration register: SCFG_SNPCNFGCR[SECRDSNP] SCFG_SNPCNFGCR[SECWRSNP] Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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@ -301,6 +301,7 @@ int arch_cpu_init(void)
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void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
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void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
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void *rcpm2_base =
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void *rcpm2_base =
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(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
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(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
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struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
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u32 state;
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u32 state;
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/*
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/*
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@ -328,6 +329,8 @@ int arch_cpu_init(void)
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*/
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*/
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fsl_epu_clean(epu_base);
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fsl_epu_clean(epu_base);
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setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
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return 0;
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return 0;
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}
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}
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@ -144,6 +144,7 @@ struct ccsr_gur {
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};
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};
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#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
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#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
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#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
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#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
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#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
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#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
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#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
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#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
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#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
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