ppc4xx: interrupt.c reworked
This patch is a rework of the 4xx interrupt handling done while adding the 460EX/GT support. Interrupts are needed on 4xx for the EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
84a999b6cd
commit
56e4101783
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@ -38,7 +38,22 @@
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DECLARE_GLOBAL_DATA_PTR;
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/****************************************************************************/
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/*
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* Define the number of UIC's
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*/
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#if defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UIC_MAX 4
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#elif defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EX)
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#define UIC_MAX 3
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#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR)
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#define UIC_MAX 2
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#else
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#define UIC_MAX 1
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#endif
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/*
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* CPM interrupt vector functions.
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@ -49,28 +64,15 @@ struct irq_action {
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int count;
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};
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static struct irq_action irq_vecs[32];
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void uic0_interrupt( void * parms); /* UIC0 handler */
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static struct irq_action irq_vecs[UIC_MAX * 32];
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#if defined(CONFIG_440) || defined(CONFIG_405EX)
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static struct irq_action irq_vecs1[32]; /* For UIC1 */
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u32 get_dcr(u16);
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void set_dcr(u16, u32);
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void uic1_interrupt( void * parms); /* UIC1 handler */
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#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
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static void uic_cascade_interrupt(void *para);
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#endif
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#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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static struct irq_action irq_vecs2[32]; /* For UIC2 */
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void uic2_interrupt( void * parms); /* UIC2 handler */
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#endif /* CONFIG_440GX CONFIG_440SPE */
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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static struct irq_action irq_vecs3[32]; /* For UIC3 */
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void uic3_interrupt( void * parms); /* UIC3 handler */
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#endif /* CONFIG_440SPE */
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#endif /* CONFIG_440 */
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/****************************************************************************/
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#if defined(CONFIG_440)
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/* SPRN changed in 440 */
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@ -99,8 +101,6 @@ static __inline__ void set_evpr(unsigned long val)
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}
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#endif /* defined(CONFIG_440 */
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/****************************************************************************/
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int interrupt_init_cpu (unsigned *decrementer_count)
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{
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int vec;
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@ -112,26 +112,10 @@ int interrupt_init_cpu (unsigned *decrementer_count)
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/*
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* Mark all irqs as free
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*/
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for (vec=0; vec<32; vec++) {
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for (vec = 0; vec < (UIC_MAX * 32); vec++) {
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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irq_vecs[vec].count = 0;
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#if defined(CONFIG_440) || defined(CONFIG_405EX)
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irq_vecs1[vec].handler = NULL;
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irq_vecs1[vec].arg = NULL;
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irq_vecs1[vec].count = 0;
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#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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irq_vecs2[vec].handler = NULL;
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irq_vecs2[vec].arg = NULL;
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irq_vecs2[vec].count = 0;
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#endif /* CONFIG_440GX */
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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irq_vecs3[vec].handler = NULL;
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irq_vecs3[vec].arg = NULL;
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irq_vecs3[vec].count = 0;
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#endif /* CONFIG_440SPE */
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#endif
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}
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#ifdef CONFIG_4xx
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@ -172,15 +156,21 @@ int interrupt_init_cpu (unsigned *decrementer_count)
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*/
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set_evpr(0x00000000);
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#if defined(CONFIG_440) || defined(CONFIG_405EX)
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#if !defined(CONFIG_440GX)
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#if (UIC_MAX > 1)
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/* Install the UIC1 handlers */
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irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
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irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
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irq_install_handler(VECNUM_UIC1NC, uic_cascade_interrupt, 0);
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irq_install_handler(VECNUM_UIC1C, uic_cascade_interrupt, 0);
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#endif
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#if (UIC_MAX > 2)
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irq_install_handler(VECNUM_UIC2NC, uic_cascade_interrupt, 0);
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irq_install_handler(VECNUM_UIC2C, uic_cascade_interrupt, 0);
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#endif
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#if defined(CONFIG_440GX)
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#if (UIC_MAX > 3)
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irq_install_handler(VECNUM_UIC3NC, uic_cascade_interrupt, 0);
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irq_install_handler(VECNUM_UIC3C, uic_cascade_interrupt, 0);
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#endif
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#else /* !defined(CONFIG_440GX) */
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/* Take the GX out of compatibility mode
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* Travis Sawyer, 9 Mar 2004
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* NOTE: 440gx user manual inconsistency here
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@ -196,457 +186,200 @@ int interrupt_init_cpu (unsigned *decrementer_count)
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mtdcr(uicb0er, 0x54000000);
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/* None are critical */
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mtdcr(uicb0cr, 0);
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#endif
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#endif /* !defined(CONFIG_440GX) */
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return (0);
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}
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/****************************************************************************/
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/* Handler for UIC interrupt */
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static void uic_interrupt(u32 uic_base, int vec_base)
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{
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u32 uic_msr;
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u32 msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = get_dcr(uic_base + UIC_MSR);
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msr_shift = uic_msr;
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vec = vec_base;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs[vec].count++;
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if (irq_vecs[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
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} else {
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set_dcr(uic_base + UIC_ER,
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get_dcr(uic_base + UIC_ER) &
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~(0x80000000 >> vec));
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printf("Masking bogus interrupt vector %d"
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" (UIC_BASE=0x%x)\n", vec, uic_base);
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}
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/*
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* After servicing the interrupt, we have to remove the status indicator.
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*/
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set_dcr(uic_base + UIC_SR, (0x80000000 >> vec));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
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static void uic_cascade_interrupt(void *para)
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{
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external_interrupt(para);
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}
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#endif
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#if defined(CONFIG_440)
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#if defined(CONFIG_440GX)
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/* 440GX uses base uic register */
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#define UIC_BMSR uicb0msr
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#define UIC_BSR uicb0sr
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#else
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#define UIC_BMSR uic0msr
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#define UIC_BSR uic0sr
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#endif
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#else /* CONFIG_440 */
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#define UIC_BMSR uicmsr
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#define UIC_BSR uicsr
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#endif /* CONFIG_440 */
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/*
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* Handle external interrupts
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*/
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#if defined(CONFIG_440GX)
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void external_interrupt(struct pt_regs *regs)
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{
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ulong uic_msr;
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u32 uic_msr;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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/* 440 GX uses base uic register */
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uic_msr = mfdcr(uicb0msr);
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uic_msr = mfdcr(UIC_BMSR);
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if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) )
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uic0_interrupt(0);
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if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
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uic1_interrupt(0);
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if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
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uic2_interrupt(0);
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mtdcr(uicb0sr, uic_msr);
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return;
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} /* external_interrupt CONFIG_440GX */
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#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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void external_interrupt(struct pt_regs *regs)
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{
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ulong uic_msr;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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/* 440 SPe uses base uic register */
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uic_msr = mfdcr(uic0msr);
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if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
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uic1_interrupt(0);
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if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
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uic2_interrupt(0);
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if (uic_msr & ~(UICB0_ALL))
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uic0_interrupt(0);
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mtdcr(uic0sr, uic_msr);
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return;
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} /* external_interrupt CONFIG_440EPX & CONFIG_440GRX */
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#elif defined(CONFIG_440SPE)
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void external_interrupt(struct pt_regs *regs)
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{
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ulong uic_msr;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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/* 440 SPe uses base uic register */
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uic_msr = mfdcr(uic0msr);
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if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
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uic1_interrupt(0);
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if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
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uic2_interrupt(0);
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if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) )
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uic3_interrupt(0);
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if (uic_msr & ~(UICB0_ALL))
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uic0_interrupt(0);
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mtdcr(uic0sr, uic_msr);
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return;
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} /* external_interrupt CONFIG_440SPE */
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#else
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void external_interrupt(struct pt_regs *regs)
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{
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ulong uic_msr;
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ulong msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = mfdcr(uicmsr);
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msr_shift = uic_msr;
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vec = 0;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs[vec].count++;
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if (irq_vecs[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
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} else {
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mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
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printf ("Masking bogus interrupt vector 0x%x\n", vec);
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}
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/*
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* After servicing the interrupt, we have to remove the status indicator.
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*/
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mtdcr(uicsr, (0x80000000 >> vec));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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#if (UIC_MAX > 1)
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if ((UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr))
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uic_interrupt(UIC1_DCR_BASE, 32);
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#endif
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#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* Handler for UIC0 interrupt */
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void uic0_interrupt( void * parms)
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{
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ulong uic_msr;
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ulong msr_shift;
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int vec;
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#if (UIC_MAX > 2)
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if ((UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr))
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uic_interrupt(UIC2_DCR_BASE, 64);
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#endif
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = mfdcr(uicmsr);
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msr_shift = uic_msr;
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vec = 0;
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#if (UIC_MAX > 3)
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if ((UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr))
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uic_interrupt(UIC3_DCR_BASE, 96);
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#endif
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs[vec].count++;
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#if defined(CONFIG_440)
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#if !defined(CONFIG_440GX)
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if (uic_msr & ~(UICB0_ALL))
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uic_interrupt(UIC0_DCR_BASE, 0);
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#else
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if ((UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr))
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uic_interrupt(UIC0_DCR_BASE, 0);
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#endif
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#else /* CONFIG_440 */
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uic_interrupt(UIC0_DCR_BASE, 0);
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#endif /* CONFIG_440 */
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if (irq_vecs[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
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} else {
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mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
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printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec);
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}
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mtdcr(UIC_BSR, uic_msr);
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/*
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* After servicing the interrupt, we have to remove the status indicator.
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*/
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mtdcr(uicsr, (0x80000000 >> vec));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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return;
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}
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#endif /* CONFIG_440GX */
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#if defined(CONFIG_440) || defined(CONFIG_405EX)
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/* Handler for UIC1 interrupt */
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void uic1_interrupt( void * parms)
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{
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ulong uic1_msr;
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ulong msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic1_msr = mfdcr(uic1msr);
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msr_shift = uic1_msr;
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vec = 0;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs1[vec].count++;
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if (irq_vecs1[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs1[vec].handler)(irq_vecs1[vec].arg);
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} else {
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mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec));
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printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
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}
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/*
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* After servicing the interrupt, we have to remove the status indicator.
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*/
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mtdcr(uic1sr, (0x80000000 >> vec));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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#endif /* defined(CONFIG_440) */
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#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* Handler for UIC2 interrupt */
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void uic2_interrupt( void * parms)
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{
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ulong uic2_msr;
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ulong msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic2_msr = mfdcr(uic2msr);
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msr_shift = uic2_msr;
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vec = 0;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs2[vec].count++;
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if (irq_vecs2[vec].handler != NULL) {
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/* call isr */
|
||||
(*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
|
||||
} else {
|
||||
mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
|
||||
printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec);
|
||||
}
|
||||
|
||||
/*
|
||||
* After servicing the interrupt, we have to remove the status indicator.
|
||||
*/
|
||||
mtdcr(uic2sr, (0x80000000 >> vec));
|
||||
}
|
||||
|
||||
/*
|
||||
* Shift msr to next position and increment vector
|
||||
*/
|
||||
msr_shift <<= 1;
|
||||
vec++;
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_440GX) */
|
||||
|
||||
#if defined(CONFIG_440SPE)
|
||||
/* Handler for UIC3 interrupt */
|
||||
void uic3_interrupt( void * parms)
|
||||
{
|
||||
ulong uic3_msr;
|
||||
ulong msr_shift;
|
||||
int vec;
|
||||
|
||||
/*
|
||||
* Read masked interrupt status register to determine interrupt source
|
||||
*/
|
||||
uic3_msr = mfdcr(uic3msr);
|
||||
msr_shift = uic3_msr;
|
||||
vec = 0;
|
||||
|
||||
while (msr_shift != 0) {
|
||||
if (msr_shift & 0x80000000) {
|
||||
/*
|
||||
* Increment irq counter (for debug purpose only)
|
||||
*/
|
||||
irq_vecs3[vec].count++;
|
||||
|
||||
if (irq_vecs3[vec].handler != NULL) {
|
||||
/* call isr */
|
||||
(*irq_vecs3[vec].handler)(irq_vecs3[vec].arg);
|
||||
} else {
|
||||
mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec));
|
||||
printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec);
|
||||
}
|
||||
|
||||
/*
|
||||
* After servicing the interrupt, we have to remove the status indicator.
|
||||
*/
|
||||
mtdcr(uic3sr, (0x80000000 >> vec));
|
||||
}
|
||||
|
||||
/*
|
||||
* Shift msr to next position and increment vector
|
||||
*/
|
||||
msr_shift <<= 1;
|
||||
vec++;
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_440SPE) */
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* Install and free a interrupt handler.
|
||||
*/
|
||||
|
||||
void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
|
||||
void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
|
||||
{
|
||||
struct irq_action *irqa = irq_vecs;
|
||||
int i = vec;
|
||||
|
||||
#if defined(CONFIG_440) || defined(CONFIG_405EX)
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
if ((vec > 31) && (vec < 64)) {
|
||||
i = vec - 32;
|
||||
irqa = irq_vecs1;
|
||||
} else if (vec > 63) {
|
||||
i = vec - 64;
|
||||
irqa = irq_vecs2;
|
||||
}
|
||||
#else /* CONFIG_440GX */
|
||||
if (vec > 31) {
|
||||
i = vec - 32;
|
||||
irqa = irq_vecs1;
|
||||
}
|
||||
#endif /* CONFIG_440GX */
|
||||
#endif /* CONFIG_440 */
|
||||
int i;
|
||||
|
||||
/*
|
||||
* print warning when replacing with a different irq vector
|
||||
* Print warning when replacing with a different irq vector
|
||||
*/
|
||||
if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) {
|
||||
printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
|
||||
vec, (uint) handler, (uint) irqa[i].handler);
|
||||
if ((irq_vecs[vec].handler != NULL) && (irq_vecs[vec].handler != handler)) {
|
||||
printf("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
|
||||
vec, (uint) handler, (uint) irq_vecs[vec].handler);
|
||||
}
|
||||
irqa[i].handler = handler;
|
||||
irqa[i].arg = arg;
|
||||
irq_vecs[vec].handler = handler;
|
||||
irq_vecs[vec].arg = arg;
|
||||
|
||||
#if defined(CONFIG_440) || defined(CONFIG_405EX)
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
if ((vec > 31) && (vec < 64))
|
||||
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
|
||||
else if (vec > 63)
|
||||
mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
|
||||
else
|
||||
#endif /* CONFIG_440GX */
|
||||
if (vec > 31)
|
||||
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
|
||||
else
|
||||
i = vec & 0x1f;
|
||||
if ((vec >= 0) && (vec < 32))
|
||||
mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
|
||||
#if (UIC_MAX > 1)
|
||||
else if ((vec >= 32) && (vec < 64))
|
||||
mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
|
||||
#endif
|
||||
mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i));
|
||||
#if 0
|
||||
printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
|
||||
#if (UIC_MAX > 2)
|
||||
else if ((vec >= 64) && (vec < 96))
|
||||
mtdcr(uic2er, mfdcr(uic2er) | (0x80000000 >> i));
|
||||
#endif
|
||||
#if (UIC_MAX > 3)
|
||||
else if (vec >= 96)
|
||||
mtdcr(uic3er, mfdcr(uic3er) | (0x80000000 >> i));
|
||||
#endif
|
||||
|
||||
debug("Install interrupt for vector %d ==> %p\n", vec, handler);
|
||||
}
|
||||
|
||||
void irq_free_handler (int vec)
|
||||
{
|
||||
struct irq_action *irqa = irq_vecs;
|
||||
int i = vec;
|
||||
int i;
|
||||
|
||||
#if defined(CONFIG_440) || defined(CONFIG_405EX)
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
if ((vec > 31) && (vec < 64)) {
|
||||
irqa = irq_vecs1;
|
||||
i = vec - 32;
|
||||
} else if (vec > 63) {
|
||||
irqa = irq_vecs2;
|
||||
i = vec - 64;
|
||||
}
|
||||
#endif /* CONFIG_440GX */
|
||||
if (vec > 31) {
|
||||
irqa = irq_vecs1;
|
||||
i = vec - 32;
|
||||
}
|
||||
debug("Free interrupt for vector %d ==> %p\n",
|
||||
vec, irq_vecs[vec].handler);
|
||||
|
||||
i = vec & 0x1f;
|
||||
if ((vec >= 0) && (vec < 32))
|
||||
mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
|
||||
#if (UIC_MAX > 1)
|
||||
else if ((vec >= 32) && (vec < 64))
|
||||
mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
|
||||
#endif
|
||||
#if (UIC_MAX > 2)
|
||||
else if ((vec >= 64) && (vec < 96))
|
||||
mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> i));
|
||||
#endif
|
||||
#if (UIC_MAX > 3)
|
||||
else if (vec >= 96)
|
||||
mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> i));
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
printf ("Free interrupt for vector %d ==> %p\n",
|
||||
vec, irq_vecs[vec].handler);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440) || defined(CONFIG_405EX)
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
if ((vec > 31) && (vec < 64))
|
||||
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
|
||||
else if (vec > 63)
|
||||
mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
|
||||
else
|
||||
#endif /* CONFIG_440GX */
|
||||
if (vec > 31)
|
||||
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
|
||||
else
|
||||
#endif
|
||||
mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i));
|
||||
|
||||
irqa[i].handler = NULL;
|
||||
irqa[i].arg = NULL;
|
||||
irq_vecs[vec].handler = NULL;
|
||||
irq_vecs[vec].arg = NULL;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
void timer_interrupt_cpu (struct pt_regs *regs)
|
||||
{
|
||||
/* nothing to do here */
|
||||
return;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_CMD_IRQ)
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* irqinfo - print information about PCI devices
|
||||
*
|
||||
*/
|
||||
int
|
||||
do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int vec;
|
||||
|
||||
printf ("\nInterrupt-Information:\n");
|
||||
#if defined(CONFIG_440) || defined(CONFIG_405EX)
|
||||
printf ("\nUIC 0\n");
|
||||
#endif
|
||||
printf ("Interrupt-Information:\n");
|
||||
printf ("Nr Routine Arg Count\n");
|
||||
|
||||
for (vec=0; vec<32; vec++) {
|
||||
for (vec = 0; vec < (UIC_MAX * 32); vec++) {
|
||||
if (irq_vecs[vec].handler != NULL) {
|
||||
printf ("%02d %08lx %08lx %d\n",
|
||||
vec,
|
||||
|
|
@ -656,46 +389,6 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_440) || defined(CONFIG_405EX)
|
||||
printf ("\nUIC 1\n");
|
||||
printf ("Nr Routine Arg Count\n");
|
||||
|
||||
for (vec=0; vec<32; vec++) {
|
||||
if (irq_vecs1[vec].handler != NULL)
|
||||
printf ("%02d %08lx %08lx %d\n",
|
||||
vec+31, (ulong)irq_vecs1[vec].handler,
|
||||
(ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count);
|
||||
}
|
||||
printf("\n");
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
printf ("\nUIC 2\n");
|
||||
printf ("Nr Routine Arg Count\n");
|
||||
|
||||
for (vec=0; vec<32; vec++) {
|
||||
if (irq_vecs2[vec].handler != NULL)
|
||||
printf ("%02d %08lx %08lx %d\n",
|
||||
vec+63, (ulong)irq_vecs2[vec].handler,
|
||||
(ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count);
|
||||
}
|
||||
printf("\n");
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440SPE)
|
||||
printf ("\nUIC 3\n");
|
||||
printf ("Nr Routine Arg Count\n");
|
||||
|
||||
for (vec=0; vec<32; vec++) {
|
||||
if (irq_vecs3[vec].handler != NULL)
|
||||
printf ("%02d %08lx %08lx %d\n",
|
||||
vec+63, (ulong)irq_vecs3[vec].handler,
|
||||
(ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count);
|
||||
}
|
||||
printf("\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue