MIPS: Malta: Enable CM & L2 support
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS Malta board, removing the need for us to attempt to bypass the L2 during boot (which would fail with recent CPUs that expose L2 config via the CM anyway). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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@ -26,6 +26,8 @@ config TARGET_MALTA
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select DM
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select DM_SERIAL
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select DYNAMIC_IO_PORT_BASE
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select MIPS_CM
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select MIPS_L2_CACHE
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select OF_CONTROL
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select OF_ISA_BUS
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select SUPPORTS_BIG_ENDIAN
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@ -28,12 +28,6 @@
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.globl lowlevel_init
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lowlevel_init:
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/* disable any L2 cache for now */
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sync
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mfc0 t0, CP0_CONFIG, 2
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ori t0, t0, 0x1 << 12
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mtc0 t0, CP0_CONFIG, 2
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/* detect the core card */
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PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
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lw t0, 0(t0)
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