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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

This commit is contained in:
Tom Rini 2016-03-22 12:14:27 -04:00
parent a119357c43 6dedcedd64
commit 55926ddd18
33 changed files with 591 additions and 334 deletions
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2
arch/arm/cpu/armv8/cache_v8.c
View File

@ -320,7 +320,7 @@ static int count_required_pts(u64 addr, int level, u64 maxaddr)
}
/* Returns the estimated required size of all page tables */
u64 get_page_table_size(void)
__weak u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
u64 size = 0;

5
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -410,6 +410,11 @@ static inline void final_mmu_setup(void)
*/
}
u64 get_page_table_size(void)
{
return 0x10000;
}
int arch_cpu_init(void)
{
icache_enable();

113
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View File

@ -73,115 +73,6 @@ void ft_fixup_cpu(void *blob)
}
#endif
/*
* the burden is on the the caller to not request a count
* exceeding the bounds of the stream_ids[] array
*/
void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt)
{
int i;
if (count > max_cnt) {
printf("\n%s: ERROR: max per-device stream ID count exceed\n",
__func__);
return;
}
for (i = 0; i < count; i++)
stream_ids[i] = start_id++;
}
/*
* This function updates the mmu-masters property on the SMMU
* node as per the SMMU binding-- phandle and list of stream IDs
* for each MMU master.
*/
void append_mmu_masters(void *blob, const char *smmu_path,
const char *master_name, u32 *stream_ids, int count)
{
u32 phandle;
int smmu_nodeoffset;
int master_nodeoffset;
int i;
/* get phandle of mmu master device */
master_nodeoffset = fdt_path_offset(blob, master_name);
if (master_nodeoffset < 0) {
printf("\n%s: ERROR: master not found\n", __func__);
return;
}
phandle = fdt_get_phandle(blob, master_nodeoffset);
if (!phandle) { /* if master has no phandle, create one */
phandle = fdt_create_phandle(blob, master_nodeoffset);
if (!phandle) {
printf("\n%s: ERROR: unable to create phandle\n",
__func__);
return;
}
}
/* append it to mmu-masters */
smmu_nodeoffset = fdt_path_offset(blob, smmu_path);
if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters",
phandle) < 0) {
printf("\n%s: ERROR: unable to update SMMU node\n", __func__);
return;
}
/* for each stream ID, append to mmu-masters */
for (i = 0; i < count; i++) {
fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters",
stream_ids[i]);
}
/* fix up #stream-id-cells with stream ID count */
if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells",
count) < 0)
printf("\n%s: ERROR: unable to update #stream-id-cells\n",
__func__);
}
/*
* The info below summarizes how streamID partitioning works
* for ls2080a and how it is conveyed to the OS via the device tree.
*
* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
* -all legacy devices get a unique ICID assigned and programmed in
* their AMQR registers by u-boot
* -u-boot updates the hardware device tree with streamID properties
* for each platform/legacy device (smmu-masters property)
*
* -PCIe
* -for each PCI controller that is active (as per RCW settings),
* u-boot will allocate a range of ICID and convey that to Linux via
* the device tree (smmu-masters property)
*
* -DPAA2
* -u-boot will allocate a range of ICIDs to be used by the Management
* Complex for containers and will set these values in the MC DPC image.
* -the MC is responsible for allocating and setting up ICIDs
* for all DPAA2 devices.
*
*/
#ifdef CONFIG_FSL_LSCH3
static void fdt_fixup_smmu(void *blob)
{
int nodeoffset;
nodeoffset = fdt_path_offset(blob, "/iommu@5000000");
if (nodeoffset < 0) {
printf("\n%s: WARNING: no SMMU node found\n", __func__);
return;
}
/* fixup for all PCI controllers */
#ifdef CONFIG_PCI
fdt_fixup_smmu_pcie(blob);
#endif
}
#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_MP
@ -204,10 +95,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_esdhc(blob, bd);
#endif
#ifdef CONFIG_FSL_LSCH3
fdt_fixup_smmu(blob);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif

4
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@ -106,9 +106,13 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
#else
sys_info->freq_sdhc = sys_info->freq_systembus;
#endif
#endif
#if defined(CONFIG_FSL_IFC)

8
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View File

@ -18,6 +18,14 @@ ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
#ifdef CONFIG_FSL_LSCH3
/* Set Wuo bit for RN-I 20 */
#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A)
ldr x0, =CCI_AUX_CONTROL_BASE(20)
ldr x1, =0x00000010
bl ccn504_set_aux
#endif
/* Add fully-coherent masters to DVM domain */
ldr x0, =CCI_MN_BASE
ldr x1, =CCI_MN_RNF_NODEID_LIST

14
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
View File

@ -14,7 +14,7 @@ struct serdes_config {
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } },
{0x03, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
{0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
{0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
SGMII1 } },
@ -31,9 +31,9 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
QSGMII_B} },
{0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
QSGMII_A} },
{0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
@ -56,10 +56,10 @@ static struct serdes_config serdes2_cfg_tbl[] = {
{0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
{0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
{0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
{0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
SGMII16 } },
{0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
{0x45, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
PCIE4 } },
{0x47, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
SGMII16 } },
{0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
SATA2 } },
{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,

3
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -91,6 +91,8 @@
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define TZPCR0SIZE_BASE (TZPC_BASE)
@ -119,6 +121,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_ERRATUM_A009635
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009803
#define CONFIG_SYS_FSL_ERRATUM_A009942
/* ARM A57 CORE ERRATA */

8
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -86,6 +86,10 @@
#define PCIE_LUT_BASE 0x80000
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
#define PCIE_LUT_ENABLE (1 << 31)
#define PCIE_LUT_ENTRY_COUNT 32
/* Device Configuration */
#define DCFG_BASE 0x01e00000
@ -98,6 +102,10 @@
#define DCFG_DCSR_BASE 0X700100000ULL
#define DCFG_DCSR_PORCR1 0x000
/* Interrupt Sampling Control */
#define ISC_BASE 0x01F70000
#define IRQCR_OFFSET 0x14
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000

55
arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
View File

@ -7,28 +7,48 @@
#ifndef __FSL_STREAM_ID_H
#define __FSL_STREAM_ID_H
/* Stream IDs on ls2080a devices are not hardwired and are
/*
* Stream IDs on ls2080a devices are not hardwired and are
* programmed by sw. There are a limited number of stream IDs
* available, and the partitioning of them is scenario dependent.
* This header defines the partitioning between legacy, PCI,
* and DPAA2 devices.
*
* This partitiong can be customized in this file depending
* on the specific hardware config-- e.g. perhaps not all
* PEX controllers are in use.
* This partitioning can be customized in this file depending
* on the specific hardware config:
*
* On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
* -all legacy devices get a unique stream ID assigned and programmed in
* their AMQR registers by u-boot
*
* -PCIe
* -there is a range of stream IDs set aside for PCI in this
* file. U-boot will scan the PCI bus and for each device discovered:
* -allocate a streamID
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
* -set a msi-map entry in the PEXn controller node in the
* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
* for more info on the msi-map definition)
*
* -DPAA2
* -u-boot will allocate a range of stream IDs to be used by the Management
* Complex for containers and will set these values in the MC DPC image.
* -the MC is responsible for allocating and setting up 'isolation context
* IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
*
* On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
* each of the different bus masters. The relationship between
* the AMQ registers and stream IDs is defined in the table below:
* AMQ bit streamID bit
* ---------------------------
* PL[18] 9
* BMT[17] 8
* VA[16] 7
* [15] -
* ICID[14:7] -
* ICID[6:0] 6-0
* PL[18] 9 // privilege bit
* BMT[17] 8 // bypass translation
* VA[16] 7 // reserved
* [15] - // unused
* ICID[14:7] - // unused
* ICID[6:0] 6-0 // isolation context id
* ----------------------------
*
*/
#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
@ -46,16 +66,9 @@
#define FSL_SATA2_STREAM_ID 5
#define FSL_DMA_STREAM_ID 6
/* PCI - programmed in PEXn_LUT by OS */
/* 4 IDs per controller */
#define FSL_PEX1_STREAM_ID_START 7
#define FSL_PEX1_STREAM_ID_END 10
#define FSL_PEX2_STREAM_ID_START 11
#define FSL_PEX2_STREAM_ID_END 14
#define FSL_PEX3_STREAM_ID_START 15
#define FSL_PEX3_STREAM_ID_END 18
#define FSL_PEX4_STREAM_ID_START 19
#define FSL_PEX4_STREAM_ID_END 22
/* PCI - programmed in PEXn_LUT */
#define FSL_PEX_STREAM_ID_START 7
#define FSL_PEX_STREAM_ID_END 22
/* DPAA2 - set in MC DPC and alloced by MC */
#define FSL_DPAA2_STREAM_ID_START 23

4
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -137,7 +137,7 @@
#endif
#define FSL_IFC_COMPAT "fsl,ifc"
#define FSL_QSPI_COMPAT "fsl,ls1-qspi"
#define FSL_DSPI_COMPAT "fsl,vf610-dspi"
#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi"
#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi"
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */

21
arch/arm/lib/ccn504.S
View File

@ -59,3 +59,24 @@ ENTRY(ccn504_set_qos)
ret
ENDPROC(ccn504_set_qos)
/*************************************************************************
*
* void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value);
*
* Initialize AUX control settings
*
*************************************************************************/
ENTRY(ccn504_set_aux)
/*
* x0: CCI_AUX_CONTROL_BASE
* x1: Value
*/
ldr x9, [x0]
mov x10, x1
orr x9, x9, x10
str x9, [x0]
ret
ENDPROC(ccn504_set_aux)

12
board/freescale/common/vid.c
View File

@ -454,6 +454,9 @@ int adjust_vdd(ulong vdd_override)
exit:
if (re_enable)
enable_interrupts();
i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
return ret;
}
@ -469,7 +472,7 @@ static int print_vdd(void)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
return -1;
goto exit;
} else {
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
@ -481,11 +484,14 @@ static int print_vdd(void)
vdd_last = read_voltage(i2caddress);
if (vdd_last < 0) {
printf("VID: Couldn't read sensor abort VID adjustment\n");
return -1;
goto exit;
}
printf("VID: Core voltage is at %d mV\n", vdd_last);
exit:
i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
return ret < 0 ? -1 : 0;
return 0;
}
static int do_vdd_override(cmd_tbl_t *cmdtp,

6
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -170,8 +170,7 @@ void board_retimer_init(void)
u8 reg;
/* Retimer is connected to I2C1_CH7_CH5 */
reg = I2C_MUX_CH7;
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
select_i2c_ch_pca9547(I2C_MUX_CH7);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
@ -219,6 +218,9 @@ void board_retimer_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
/* Return the default channel */
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}
int board_early_init_f(void)

25
board/freescale/ls2080aqds/eth.c
View File

@ -548,12 +548,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
dpmac_info[dpmac_id].phydev = phy_connect(
dpmac_info[dpmac_id].bus,
dpmac_info[dpmac_id].phy_addr,
NULL,
dpmac_info[dpmac_id].enet_if);
phy_config(dpmac_info[dpmac_id].phydev);
break;
case 2:
/* Slot housing a SGMII riser card? */
@ -562,12 +556,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
bus = mii_dev_for_muxval(EMI1_SLOT2);
wriop_set_mdio(dpmac_id, bus);
dpmac_info[dpmac_id].phydev = phy_connect(
dpmac_info[dpmac_id].bus,
dpmac_info[dpmac_id].phy_addr,
NULL,
dpmac_info[dpmac_id].enet_if);
phy_config(dpmac_info[dpmac_id].phydev);
break;
case 3:
break;
@ -606,12 +594,6 @@ serdes2:
dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
bus = mii_dev_for_muxval(EMI1_SLOT4);
wriop_set_mdio(dpmac_id, bus);
dpmac_info[dpmac_id].phydev = phy_connect(
dpmac_info[dpmac_id].bus,
dpmac_info[dpmac_id].phy_addr,
NULL,
dpmac_info[dpmac_id].enet_if);
phy_config(dpmac_info[dpmac_id].phydev);
break;
case 5:
break;
@ -679,13 +661,6 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
dpmac_info[dpmac_id].phydev = phy_connect(
dpmac_info[dpmac_id].bus,
dpmac_info[dpmac_id].phy_addr,
NULL,
dpmac_info[dpmac_id].enet_if);
phy_config(dpmac_info[dpmac_id].phydev);
break;
case 3:
break;

39
board/freescale/ls2080ardb/eth_ls2080rdb.c
View File

@ -20,42 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
int load_firmware_cortina(struct phy_device *phy_dev)
{
if (phy_dev->drv->config)
return phy_dev->drv->config(phy_dev);
return 0;
}
void load_phy_firmware(void)
{
int i;
u8 phy_addr;
struct phy_device *phy_dev;
struct mii_dev *dev;
phy_interface_t interface;
/*Initialize and upload firmware for all the PHYs*/
for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
interface = wriop_get_enet_if(i);
if (interface == PHY_INTERFACE_MODE_XGMII) {
dev = wriop_get_mdio(i);
phy_addr = wriop_get_phy_address(i);
phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
interface);
if (!phy_dev) {
printf("No phydev for phyaddr %d\n", phy_addr);
continue;
}
/*Flash firmware for All CS4340 PHYS */
if (phy_dev->phy_id == PHY_UID_CS4340)
load_firmware_cortina(phy_dev);
}
}
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
@ -125,9 +89,6 @@ int board_eth_init(bd_t *bis)
}
}
/* Load CORTINA CS4340 PHY firmware */
load_phy_firmware();
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */

4
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -149,6 +149,7 @@ int board_init(void)
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
u32 val;
init_final_memctl_regs();
@ -170,6 +171,9 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
return 0;
}

9
doc/README.fsl-ddr
View File

@ -123,6 +123,14 @@ ECC can be turned on/off by hwconfig.
Syntax is
hwconfig=fsl_ddr:ecc=off
Memory address parity on/off
============================
address parity can be turned on/off by hwconfig.
Syntax is:
hwconfig=fsl_ddr:parity=on
Memory testing options for mpc85xx
==================================
1. Memory test can be done once U-Boot prompt comes up using mtest, or
@ -143,6 +151,7 @@ platform
hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
Table for dynamic ODT for DDR3
==============================
For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may

80
drivers/crypto/fsl/desc.h
View File

@ -436,6 +436,31 @@
#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT)
#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT)
#define OP_PCLID_DSA_SIGN (0x15 << OP_PCLID_SHIFT)
#define OP_PCLID_DSA_VERIFY (0x16 << OP_PCLID_SHIFT)
/* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL */
#define OP_PCLID_MP_PUB_KEY (0x14 << OP_PCLID_SHIFT)
#define OP_PCLID_MP_SIGN (0x15 << OP_PCLID_SHIFT)
/* Assuming OP_TYPE = OP_TYPE_ENCAP_PROTOCOL */
#define OP_PCLID_MP_PRIV_KEY (0x14 << OP_PCLID_SHIFT)
/* PROTINFO fields for discrete log public key protocols */
#define OP_PROTINFO_F2M_FP 0x00000001
#define OP_PROTINFO_ECC_DL 0x00000002
#define OP_PROTINFO_ENC_PRI 0x00000004
#define OP_PROTINFO_TEST 0x00000008
#define OP_PROTINFO_EXT_PRI 0x00000010
#define OP_PROTINFO_ENC_Z 0x00000020
#define OP_PROTINFO_EKT_Z 0x00000040
#define OP_PROTINFO_MES_REP 0x00000400
#define OP_PROTINFO_HASH_MD5 0x00000000
#define OP_PROTINFO_HASH_SHA1 0x00000080
#define OP_PROTINFO_HASH_SHA224 0x00000100
#define OP_PROTINFO_HASH_SHA256 0x00000180
#define OP_PROTINFO_HASH_SHA384 0x00000200
#define OP_PROTINFO_HASH_SHA512 0x00000280
/* For non-protocol/alg-only op commands */
#define OP_ALG_TYPE_SHIFT 24
@ -663,4 +688,59 @@
#define OP_ALG_RNG4_MAS (0x1f3 << OP_ALG_RNG4_SHIFT)
#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT)
/* Structures for Protocol Data Blocks */
struct __packed pdb_ecdsa_verify {
uint32_t pdb_hdr;
dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */
dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */
dma_addr_t dma_hash; /* Pointer to hash input */
dma_addr_t dma_c; /* Pointer to C_signature */
dma_addr_t dma_d; /* Pointer to D_signature */
dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */
dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
uint32_t img_size; /* Length of Message */
};
struct __packed pdb_ecdsa_sign {
uint32_t pdb_hdr;
dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */
dma_addr_t dma_pri_key; /* Pointer to S (Private key) */
dma_addr_t dma_hash; /* Pointer to hash input */
dma_addr_t dma_c; /* Pointer to C_signature */
dma_addr_t dma_d; /* Pointer to D_signature */
dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
dma_addr_t dma_u; /* Pointer to Per Message Random */
uint32_t img_size; /* Length of Message */
};
#define PDB_ECDSA_SGF_SHIFT 23
#define PDB_ECDSA_L_SHIFT 7
#define PDB_ECDSA_N_SHIFT 0
struct __packed pdb_mp_pub_k {
uint32_t pdb_hdr;
#define PDB_MP_PUB_K_SGF_SHIFT 31
dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */
};
struct __packed pdb_mp_sign {
uint32_t pdb_hdr;
#define PDB_MP_SIGN_SGF_SHIFT 28
dma_addr_t dma_addr_msg; /* Pointer to Message */
dma_addr_t dma_addr_hash; /* Pointer to hash output */
dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */
dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */
uint32_t img_size; /* Length of Message */
};
#define PDB_MP_CSEL_SHIFT 17
#define PDB_MP_CSEL_P256 0x3 << PDB_MP_CSEL_SHIFT /* P-256 */
#define PDB_MP_CSEL_P384 0x4 << PDB_MP_CSEL_SHIFT /* P-384 */
#define PDB_MP_CSEL_P521 0x5 << PDB_MP_CSEL_SHIFT /* P-521 */
#endif /* DESC_H */

27
drivers/crypto/fsl/desc_constr.h
View File

@ -53,6 +53,19 @@ union ptr_addr_t {
};
#endif
static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr)
{
#ifdef CONFIG_PHYS_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
ptr_addr->m_halfs.high = (u32)(ptr >> 32);
ptr_addr->m_halfs.low = (u32)ptr;
#else
*offset = ptr;
#endif
}
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@ -68,6 +81,11 @@ static inline u32 *desc_end(u32 *desc)
return desc + desc_len(desc);
}
static inline void *desc_pdb(u32 *desc)
{
return desc + 1;
}
static inline void init_desc(u32 *desc, u32 options)
{
*desc = (options | HDR_ONE) + 1;
@ -78,6 +96,15 @@ static inline void init_job_desc(u32 *desc, u32 options)
init_desc(desc, CMD_DESC_HDR | options);
}
static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
{
u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
init_job_desc(desc,
(((pdb_len + 1) << HDR_START_IDX_SHIFT) + pdb_len) |
options);
}
static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);

2
drivers/crypto/fsl/jr.c
View File

@ -360,7 +360,7 @@ int run_descriptor_jr(uint32_t *desc)
}
}
if (!op.status) {
if (op.status) {
debug("Error %x\n", op.status);
ret = op.status;
}

55
drivers/ddr/fsl/ctrl_regs.c
View File

@ -895,11 +895,15 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
slow = get_ddr_freq(ctrl_num) < 1249000000;
#endif
if (popts->registered_dimm_en) {
if (popts->registered_dimm_en)
rcw_en = 1;
ap_en = popts->ap_en;
} else {
/* DDR4 can have address parity for UDIMM and discrete */
if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
(!popts->registered_dimm_en)) {
ap_en = 0;
} else {
ap_en = popts->ap_en;
}
x4_en = popts->x4_en ? 1 : 0;
@ -1135,6 +1139,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
unsigned short esdmode5; /* Extended SDRAM mode 5 */
int rtt_park = 0;
bool four_cs = false;
const unsigned int mclk_ps = get_memory_clk_period_ps(0);
#if CONFIG_CHIP_SELECTS_PER_CTRL == 4
if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
@ -1150,6 +1155,19 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
esdmode5 = 0x00000400; /* Data mask enabled */
}
/* set command/address parity latency */
if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
if (mclk_ps >= 935) {
/* for DDR4-1600/1866/2133 */
esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
} else if (mclk_ps >= 833) {
/* for DDR4-2400 */
esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
} else {
printf("parity: mclk_ps = %d not supported\n", mclk_ps);
}
}
ddr->ddr_sdram_mode_9 = (0
| ((esdmode4 & 0xffff) << 16)
| ((esdmode5 & 0xffff) << 0)
@ -1170,6 +1188,20 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
} else {
esdmode5 = 0x00000400;
}
if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
if (mclk_ps >= 935) {
/* for DDR4-1600/1866/2133 */
esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
} else if (mclk_ps >= 833) {
/* for DDR4-2400 */
esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
} else {
printf("parity: mclk_ps = %d not supported\n",
mclk_ps);
}
}
switch (i) {
case 1:
ddr->ddr_sdram_mode_11 = (0
@ -1925,12 +1957,25 @@ static void set_timing_cfg_7(const unsigned int ctrl_num,
const common_timing_params_t *common_dimm)
{
unsigned int txpr, tcksre, tcksrx;
unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
par_lat = 0;
if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
if (mclk_ps >= 935) {
/* parity latency 4 clocks in case of 1600/1866/2133 */
par_lat = 4;
} else if (mclk_ps >= 833) {
/* parity latency 5 clocks for DDR4-2400 */
par_lat = 5;
} else {
printf("parity: mclk_ps = %d not supported\n", mclk_ps);
}
}
cs_to_cmd = 0;
if (txpr <= 200)

44
drivers/ddr/fsl/fsl_ddr_gen4.c
View File

@ -12,7 +12,8 @@
#include <fsl_ddr.h>
#include <fsl_errata.h>
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
defined(CONFIG_SYS_FSL_ERRATUM_A009803)
static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
{
int timeout = 1000;
@ -24,9 +25,9 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
timeout--;
}
if (timeout <= 0)
puts("Error: A007865 wait for clear timeout.\n");
puts("Error: wait for clear timeout.\n");
}
#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@ -201,7 +202,18 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
/* part 1 of 2 */
if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
ddr_out32(&ddr->ddr_sdram_rcw_2,
regs->ddr_sdram_rcw_2 & ~0x0f000000);
}
ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
#else
ddr_out32(&ddr->err_disable, regs->err_disable);
#endif
ddr_out32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++) {
if (regs->debug[i]) {
@ -297,7 +309,8 @@ step2:
mb();
isb();
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
defined(CONFIG_SYS_FSL_ERRATUM_A009803)
/* Part 2 of 2 */
/* This erraum only applies to verion 5.2.0 */
if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
@ -313,6 +326,7 @@ step2:
ctrl_num, ddr_in32(&ddr->debug[1]));
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
/* The vref setting sequence is different for range 2 */
if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
vref_seq = vref_seq2;
@ -359,9 +373,29 @@ step2:
}
/* Restore D_INIT */
ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
}
#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
/* if it's RDIMM */
if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
continue;
set_wait_for_bits_clear(&ddr->sdram_md_cntl,
MD_CNTL_MD_EN |
MD_CNTL_CS_SEL(i) |
0x070000ed,
MD_CNTL_MD_EN);
udelay(1);
}
}
ddr_out32(&ddr->err_disable,
regs->err_disable & ~DDR_ERR_DISABLE_APED);
#endif
}
#endif
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (!(regs->cs[i].config & 0x80000000))

15
drivers/ddr/fsl/options.c
View File

@ -1002,8 +1002,19 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
popts->twot_en = 0;
popts->threet_en = 0;
/* for RDIMM, address parity enable */
popts->ap_en = 1;
/* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
if (popts->registered_dimm_en)
popts->ap_en = 1; /* 0 = disable, 1 = enable */
else
popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
if (popts->registered_dimm_en ||
(CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
popts->ap_en = 1;
}
}
/*
* BSTTOPRE precharge interval

3
drivers/net/fsl-mc/mc.c
View File

@ -1147,7 +1147,8 @@ int fsl_mc_ldpaa_exit(bd_t *bd)
{
int err = 0;
if (bd && get_mc_boot_status() == -1)
/* MC is not loaded intentionally, So return success. */
if (bd && get_mc_boot_status() != 0)
return 0;
if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {

121
drivers/net/ldpaa_eth/ldpaa_eth.c
View File

@ -14,15 +14,32 @@
#include <linux/compat.h>
#include <fsl-mc/fsl_dpmac.h>
#include <fsl-mc/ldpaa_wriop.h>
#include "ldpaa_eth.h"
#undef CONFIG_PHYLIB
#ifdef CONFIG_PHYLIB
static int init_phy(struct eth_device *dev)
{
/*TODO for external PHY */
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
struct phy_device *phydev = NULL;
struct mii_dev *bus;
return 0;
bus = wriop_get_mdio(priv->dpmac_id);
if (bus == NULL)
return 0;
phydev = phy_connect(bus, wriop_get_phy_address(priv->dpmac_id),
dev, wriop_get_enet_if(priv->dpmac_id));
if (!phydev) {
printf("Failed to connect\n");
return -1;
}
priv->phydev = phydev;
return phy_config(phydev);
}
#endif
#ifdef DEBUG
static void ldpaa_eth_get_dpni_counter(void)
@ -380,7 +397,9 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
#ifdef DEBUG
struct dpni_link_state link_state;
#endif
int err;
int err = 0;
struct mii_dev *bus;
phy_interface_t enet_if;
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
@ -394,11 +413,48 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
printf("ERROR (DPL is deployed. No device available)\n");
return -ENODEV;
}
/* DPMAC initialization */
err = ldpaa_dpmac_setup(priv);
if (err < 0)
goto err_dpmac_setup;
#ifdef CONFIG_PHYLIB
if (priv->phydev)
err = phy_startup(priv->phydev);
if (err) {
printf("%s: Could not initialize\n",
priv->phydev->dev->name);
goto err_dpamc_bind;
}
#else
priv->phydev = (struct phy_device *)malloc(sizeof(struct phy_device));
memset(priv->phydev, 0, sizeof(struct phy_device));
priv->phydev->speed = SPEED_1000;
priv->phydev->link = 1;
priv->phydev->duplex = DUPLEX_FULL;
#endif
bus = wriop_get_mdio(priv->dpmac_id);
enet_if = wriop_get_enet_if(priv->dpmac_id);
if ((bus == NULL) &&
(enet_if == PHY_INTERFACE_MODE_XGMII)) {
priv->phydev = (struct phy_device *)
malloc(sizeof(struct phy_device));
memset(priv->phydev, 0, sizeof(struct phy_device));
priv->phydev->speed = SPEED_10000;
priv->phydev->link = 1;
priv->phydev->duplex = DUPLEX_FULL;
}
if (!priv->phydev->link) {
printf("%s: No link.\n", priv->phydev->dev->name);
err = -1;
goto err_dpamc_bind;
}
/* DPMAC binding DPNI */
err = ldpaa_dpmac_bind(priv);
if (err)
@ -425,28 +481,24 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
return err;
}
#ifdef CONFIG_PHYLIB
/* TODO Check this path */
err = phy_startup(priv->phydev);
if (err) {
printf("%s: Could not initialize\n", priv->phydev->dev->name);
return err;
}
#else
priv->phydev->speed = SPEED_1000;
priv->phydev->link = 1;
priv->phydev->duplex = DUPLEX_FULL;
#endif
err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0) {
printf("dpni_enable() failed\n");
return err;
}
dpmac_link_state.rate = SPEED_1000;
dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG;
dpmac_link_state.up = 1;
dpmac_link_state.rate = priv->phydev->speed;
if (priv->phydev->autoneg == AUTONEG_DISABLE)
dpmac_link_state.options &= ~DPMAC_LINK_OPT_AUTONEG;
else
dpmac_link_state.options |= DPMAC_LINK_OPT_AUTONEG;
if (priv->phydev->duplex == DUPLEX_HALF)
dpmac_link_state.options |= DPMAC_LINK_OPT_HALF_DUPLEX;
dpmac_link_state.up = priv->phydev->link;
err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
priv->dpmac_handle, &dpmac_link_state);
if (err < 0) {
@ -484,10 +536,7 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
goto err_qdid;
}
if (!priv->phydev->link)
printf("%s: No link.\n", priv->phydev->dev->name);
return priv->phydev->link ? 0 : -1;
return priv->phydev->link;
err_qdid:
err_rx_flow:
@ -495,9 +544,10 @@ err_rx_flow:
err_dpni_bind:
ldpaa_dpbp_free();
err_dpbp_setup:
err_dpamc_bind:
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_dpni_setup:
err_dpamc_bind:
dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
err_dpmac_setup:
return err;
}
@ -506,6 +556,9 @@ static void ldpaa_eth_stop(struct eth_device *net_dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
int err = 0;
#ifdef CONFIG_PHYLIB
struct mii_dev *bus = wriop_get_mdio(priv->dpmac_id);
#endif
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
@ -531,7 +584,10 @@ static void ldpaa_eth_stop(struct eth_device *net_dev)
printf("dpni_disable() failed\n");
#ifdef CONFIG_PHYLIB
phy_shutdown(priv->phydev);
if (priv->phydev && bus != NULL)
phy_shutdown(priv->phydev);
else
free(priv->phydev);
#endif
ldpaa_dpbp_free();
@ -914,15 +970,12 @@ static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
net_dev->halt = ldpaa_eth_stop;
net_dev->send = ldpaa_eth_tx;
net_dev->recv = ldpaa_eth_pull_dequeue_rx;
/*
TODO: PHY MDIO information
priv->bus = info->bus;
priv->phyaddr = info->phy_addr;
priv->enet_if = info->enet_if;
*/
if (init_phy(net_dev))
return 0;
#ifdef CONFIG_PHYLIB
err = init_phy(net_dev);
if (err < 0)
return err;
#endif
err = eth_register(net_dev);
if (err < 0) {

217
drivers/pci/pcie_layerscape.c
View File

@ -93,6 +93,7 @@ struct ls_pcie {
void __iomem *dbi;
void __iomem *va_cfg0;
void __iomem *va_cfg1;
int next_lut_index;
struct pci_controller hose;
};
@ -482,6 +483,147 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
}
}
#ifdef CONFIG_FSL_LSCH3
/*
* Return next available LUT index.
*/
static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
{
if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
return pcie->next_lut_index++;
else
return -1; /* LUT is full */
}
/*
* Program a single LUT entry
*/
static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
u32 streamid)
{
void __iomem *lut;
lut = pcie->dbi + PCIE_LUT_BASE;
/* leave mask as all zeroes, want to match all bits */
writel((devid << 16), lut + PCIE_LUT_UDR(index));
writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
}
/* returns the next available streamid */
static u32 ls_pcie_next_streamid(void)
{
static int next_stream_id = FSL_PEX_STREAM_ID_START;
if (next_stream_id > FSL_PEX_STREAM_ID_END)
return 0xffffffff;
return next_stream_id++;
}
/*
* An msi-map is a property to be added to the pci controller
* node. It is a table, where each entry consists of 4 fields
* e.g.:
*
* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
*/
static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
u32 devid, u32 streamid)
{
char pcie_path[19];
u32 *prop;
u32 phandle;
int nodeoffset;
/* find pci controller node */
snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
(u64)pcie->dbi);
nodeoffset = fdt_path_offset(blob, pcie_path);
if (nodeoffset < 0) {
printf("\n%s: ERROR: unable to update PCIe node: %s\n",
__func__, pcie_path);
return;
}
/* get phandle to MSI controller */
prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
if (prop == NULL) {
printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
pcie_path);
return;
}
phandle = be32_to_cpu(*prop);
/* set one msi-map row */
fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
}
static void fdt_fixup_pcie(void *blob)
{
unsigned int found_multi = 0;
unsigned char header_type;
int index;
u32 streamid;
pci_dev_t dev;
int bus;
unsigned short id;
struct pci_controller *hose;
struct ls_pcie *pcie;
int i;
for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
pcie = hose->priv_data;
for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
for (dev = PCI_BDF(bus, 0, 0);
dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
PCI_MAX_PCI_FUNCTIONS - 1);
dev += PCI_BDF(0, 0, 1)) {
if (PCI_FUNC(dev) && !found_multi)
continue;
pci_read_config_word(dev, PCI_VENDOR_ID, &id);
pci_read_config_byte(dev, PCI_HEADER_TYPE,
&header_type);
if ((id == 0xFFFF) || (id == 0x0000))
continue;
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
streamid = ls_pcie_next_streamid();
if (streamid == 0xffffffff) {
printf("ERROR: no stream ids free\n");
continue;
}
index = ls_pcie_next_lut_index(pcie);
if (index < 0) {
printf("ERROR: no LUT indexes free\n");
continue;
}
/* map PCI b.d.f to streamID in LUT */
ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
streamid);
/* update msi-map in device tree */
fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
streamid);
}
}
}
}
#endif
int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
{
struct ls_pcie *pcie;
@ -513,6 +655,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
pcie->va_cfg1 = map_physmem(info->cfg1_phys,
info->cfg1_size,
MAP_NOCACHE);
pcie->next_lut_index = 0;
/* outbound memory */
pci_set_region(&hose->regions[0],
@ -657,6 +800,10 @@ void ft_pci_setup(void *blob, bd_t *bd)
#ifdef CONFIG_PCIE4
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
#endif
#ifdef CONFIG_FSL_LSCH3
fdt_fixup_pcie(blob);
#endif
}
#else
@ -664,73 +811,3 @@ void ft_pci_setup(void *blob, bd_t *bd)
{
}
#endif
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
void pcie_set_available_streamids(void *blob, const char *pcie_path,
u32 *stream_ids, int count)
{
int nodeoffset;
int i;
nodeoffset = fdt_path_offset(blob, pcie_path);
if (nodeoffset < 0) {
printf("\n%s: ERROR: unable to update PCIe node\n", __func__);
return;
}
/* for each stream ID, append to mmu-masters */
for (i = 0; i < count; i++) {
fdt_appendprop_u32(blob, nodeoffset, "available-stream-ids",
stream_ids[i]);
}
}
#define MAX_STREAM_IDS 4
void fdt_fixup_smmu_pcie(void *blob)
{
int count;
u32 stream_ids[MAX_STREAM_IDS];
u32 ctlr_streamid = 0x300;
#ifdef CONFIG_PCIE1
/* PEX1 stream ID fixup */
count = FSL_PEX1_STREAM_ID_END - FSL_PEX1_STREAM_ID_START + 1;
alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count);
append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000",
&ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE2
/* PEX2 stream ID fixup */
count = FSL_PEX2_STREAM_ID_END - FSL_PEX2_STREAM_ID_START + 1;
alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count);
append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000",
&ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE3
/* PEX3 stream ID fixup */
count = FSL_PEX3_STREAM_ID_END - FSL_PEX3_STREAM_ID_START + 1;
alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count);
append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000",
&ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE4
/* PEX4 stream ID fixup */
count = FSL_PEX4_STREAM_ID_END - FSL_PEX4_STREAM_ID_START + 1;
alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count);
append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000",
&ctlr_streamid, 1);
#endif
}
#endif

1
include/configs/ls1021aqds.h
View File

@ -478,6 +478,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0

1
include/configs/ls1021atwr.h
View File

@ -336,6 +336,7 @@
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM 1

10
include/configs/ls1043aqds.h
View File

@ -114,6 +114,16 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1

2
include/configs/ls2080a_common.h
View File

@ -260,7 +260,7 @@ unsigned long long get_qixis_addr(void);
" 0x580800000 \0"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500" \
"earlycon=uart8250,mmio,0x21c0500 " \
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \

3
include/configs/ls2080ardb.h
View File

@ -333,7 +333,7 @@ unsigned long get_board_sys_clk(void);
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0600" \
"earlycon=uart8250,mmio,0x21c0600 " \
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
@ -355,6 +355,7 @@ unsigned long get_board_sys_clk(void);
#define AQ_PHY_ADDR2 0x01
#define AQ_PHY_ADDR3 0x02
#define AQ_PHY_ADDR4 0x03
#define AQR405_IRQ_MASK 0x36
#define CONFIG_MII
#define CONFIG_ETHPRIME "DPNI1"

11
include/fsl_ddr_sdram.h
View File

@ -123,6 +123,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG2_D_INIT 0x00000010
#define SDRAM_CFG2_AP_EN 0x00000020
#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
#define SDRAM_CFG2_ODT_NEVER 0
#define SDRAM_CFG2_ODT_ONLY_WRITE 1
@ -177,6 +178,14 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
#define DDR_CDR2_VREF_RANGE_2 0x00000040
/* DDR ERR_DISABLE */
#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
/* Mode Registers */
#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
#ifdef CONFIG_SYS_FSL_DDR3L
@ -343,7 +352,7 @@ typedef struct memctl_options_s {
/* mirrior DIMMs for DDR3 */
unsigned int mirrored_dimm;
unsigned int quad_rank_present;
unsigned int ap_en; /* address parity enable for RDIMM */
unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
unsigned int x4_en; /* enable x4 devices */
/* Global Timing Parameters */

1
include/pci.h
View File

@ -700,6 +700,7 @@ extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
extern void pci_register_hose(struct pci_controller* hose);
extern struct pci_controller* pci_bus_to_hose(int bus);
extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
extern struct pci_controller *pci_get_hose_head(void);
extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
extern int pci_hose_scan(struct pci_controller *hose);