Cleanup of the monahans cpu and delta board port.
This commit is contained in:
Markus Klotzbuecher
Markus Klotzb�cher
parent
e443c944cf
commit
552fc624f2
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@ -1,10 +1,5 @@
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/*
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* Most of this taken from Redboot hal_platform_setup.h with cleanup
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*
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* NOTE: I haven't clean this up considerably, just enough to get it
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* running. See hal_platform_setup.h for the source. See
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* board/cradle/lowlevel_init.S for another PXA250 setup that is
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* much cleaner.
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* (C) Copyright 2006 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -31,14 +26,6 @@
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DRAM_SIZE: .long CFG_DRAM_SIZE
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/* wait for coprocessor write complete */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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.macro wait time
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ldr r2, =OSCR
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mov r3, #0
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@ -49,13 +36,9 @@ DRAM_SIZE: .long CFG_DRAM_SIZE
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bls 0b
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.endm
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/*
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* Memory setup
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*/
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.globl lowlevel_init
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lowlevel_init:
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/* Set up GPIO pins first ----------------------------------------- */
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/* Set up GPIO pins first */
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mov r10, lr
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/* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
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@ -73,22 +56,7 @@ lowlevel_init:
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bic r1, r1, #0x80000000
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str r1, [r0]
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/* ---------------------------------------------------------------- */
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/* Enable memory interface */
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/* ---------------------------------------------------------------- */
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/* ---------------------------------------------------------------- */
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/* Step 1: Wait for at least 200 microsedonds to allow internal */
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/* clocks to settle. Only necessary after hard reset... */
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/* FIXME: can be optimized later */
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/* ---------------------------------------------------------------- */
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; wait #300
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mem_init:
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#define NEW_SDRAM_INIT 1
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#ifdef NEW_SDRAM_INIT
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/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
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ldr r0, =ACCR
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ldr r1, [r0]
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@ -140,121 +108,6 @@ mem_init:
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orr r1, r1, #MDCNFG_DMCEN
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str r1, [r0]
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#else /* NEW_SDRAM_INIT */
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/* configure the MEMCLKCFG register */
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ldr r1, =MEMCLKCFG
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ldr r2, =0x00010001
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set CSADRCFG[0] to data flash SRAM mode */
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ldr r1, =CSADRCFG0
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ldr r2, =0x00320809
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set CSADRCFG[1] to data flash SRAM mode */
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ldr r1, =CSADRCFG1
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ldr r2, =0x00320809
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set MSC 0 register for SRAM memory */
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ldr r1, =MSC0
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ldr r2, =0x11191119
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set CSADRCFG[2] to data flash SRAM mode */
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ldr r1, =CSADRCFG2
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ldr r2, =0x00320809
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set CSADRCFG[3] to VLIO mode */
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ldr r1, =CSADRCFG3
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ldr r2, =0x0032080B
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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/* set MSC 1 register for VLIO memory */
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ldr r1, =MSC1
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ldr r2, =0x123C1119
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
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#if 0
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/* This does not work in Zylonite. -SC */
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ldr r0, =0x15fffff0
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ldr r1, =0xb10b
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str r1, [r0]
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str r1, [r0, #4]
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#endif
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/* Configure ACCR Register */
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ldr r0, =ACCR @ ACCR
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ldr r1, =0x0180b108
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str r1, [r0]
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ldr r1, [r0]
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/* Configure MDCNFG Register */
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ldr r0, =MDCNFG @ MDCNFG
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ldr r1, =0x403
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str r1, [r0]
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ldr r1, [r0]
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/* Perform Resistive Compensation by configuring RCOMP register */
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ldr r1, =RCOMP @ RCOMP
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ldr r2, =0x000000ff
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str r2, [r1]
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ldr r2, [r1]
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/* Configure MDMRS Register for SDCS0 */
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ldr r1, =MDMRS @ MDMRS
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ldr r2, =0x60000023
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ldr r3, [r1]
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orr r2, r2, r3
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str r2, [r1]
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ldr r2, [r1]
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/* Configure MDMRS Register for SDCS1 */
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ldr r1, =MDMRS @ MDMRS
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ldr r2, =0xa0000023
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ldr r3, [r1]
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orr r2, r2, r3
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str r2, [r1]
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ldr r2, [r1]
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/* Configure MDREFR */
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ldr r1, =MDREFR @ MDREFR
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ldr r2, =0x00000006
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str r2, [r1]
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ldr r2, [r1]
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/* Configure EMPI */
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ldr r1, =EMPI @ EMPI
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ldr r2, =0x80000000
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str r2, [r1]
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ldr r2, [r1]
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/* Hardware DDR Read-Strobe Delay Calibration */
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ldr r0, =DDR_HCAL @ DDR_HCAL
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ldr r1, =0x803ffc07 @ the offset is correct? -SC
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str r1, [r0]
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wait #5
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ldr r1, [r0]
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/* Here we assume the hardware calibration alwasy be successful. -SC */
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/* Set DMCEN bit in MDCNFG Register */
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ldr r0, =MDCNFG @ MDCNFG
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ldr r1, [r0]
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orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
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str r1, [r0]
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#endif /* NEW_SDRAM_INIT */
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#ifndef CFG_SKIP_DRAM_SCRUB
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/* scrub/init SDRAM if enabled/present */
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ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */
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@ -290,96 +143,4 @@ mem_init:
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mcr p14,0,r0,c10,c0,0 /* dcsr */
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endlowlevel_init:
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mov pc, lr
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/*
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@********************************************************************************
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@ DDR calibration
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@
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@ This function is used to calibrate DQS delay lines.
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@ Monahans supports three ways to do it. One is software
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@ calibration. Two is hardware calibration. Three is hybrid
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@ calibration.
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@
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@ TBD
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@ -SC
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ddr_calibration:
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@ Case 1: Write the correct delay value once
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@ Configure DDR_SCAL Register
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ldr r0, =DDR_SCAL @ DDR_SCAL
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q ldr r1, =0xaf2f2f2f
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str r1, [r0]
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ldr r1, [r0]
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*/
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/* @ Case 2: Software Calibration
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@ Write test pattern to memory
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ldr r5, =0x0faf0faf @ Data Pattern
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ldr r4, =0xa0000000 @ DDR ram
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str r5, [r4]
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mov r1, =0x0 @ delay count
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mov r6, =0x0
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mov r7, =0x0
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ddr_loop1:
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add r1, r1, =0x1
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cmp r1, =0xf
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ble end_loop
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mov r3, r1
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mov r0, r1, lsl #30
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orr r3, r3, r0
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mov r0, r1, lsl #22
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orr r3, r3, r0
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mov r0, r1, lsl #14
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orr r3, r3, r0
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orr r3, r3, =0x80000000
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ldr r2, =DDR_SCAL
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str r3, [r2]
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ldr r2, [r4]
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cmp r2, r5
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bne ddr_loop1
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mov r6, r1
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ddr_loop2:
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add r1, r1, =0x1
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cmp r1, =0xf
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ble end_loop
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mov r3, r1
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mov r0, r1, lsl #30
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orr r3, r3, r0
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mov r0, r1, lsl #22
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orr r3, r3, r0
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mov r0, r1, lsl #14
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orr r3, r3, r0
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orr r3, r3, =0x80000000
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ldr r2, =DDR_SCAL
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str r3, [r2]
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ldr r2, [r4]
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cmp r2, r5
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be ddr_loop2
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mov r7, r2
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add r3, r6, r7
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lsr r3, r3, =0x1
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mov r0, r1, lsl #30
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orr r3, r3, r0
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mov r0, r1, lsl #22
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orr r3, r3, r0
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mov r0, r1, lsl #14
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orr r3, r3, r0
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orr r3, r3, =0x80000000
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ldr r2, =DDR_SCAL
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end_loop:
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@ Case 3: Hardware Calibratoin
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ldr r0, =DDR_HCAL @ DDR_HCAL
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ldr r1, =0x803ffc07 @ the offset is correct? -SC
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str r1, [r0]
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wait #5
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ldr r1, [r0]
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mov pc, lr
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*/
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@ -293,11 +293,6 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
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{
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unsigned long ndsr=0, event=0;
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/* mk@tbd set appropriate timeouts */
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/* if (state == FL_ERASING) */
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/* timeo = CFG_HZ * 400; */
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/* else */
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/* timeo = CFG_HZ * 20; */
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if(state == FL_WRITING) {
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event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
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} else if(state == FL_ERASING) {
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@ -569,7 +564,6 @@ void board_nand_init(struct nand_chip *nand)
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nand->hwcontrol = dfc_hwcontrol;
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/* nand->dev_ready = dfc_device_ready; */
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nand->eccmode = NAND_ECC_SOFT;
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nand->chip_delay = NAND_DELAY_US;
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nand->options = NAND_BUSWIDTH_16;
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nand->waitfunc = dfc_wait;
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nand->read_byte = dfc_read_byte;
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@ -921,9 +921,10 @@ typedef void (*ExcpHndlr) (void) ;
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#ifdef CONFIG_CPU_MONAHANS
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#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
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/* Missing: 32 Interrupt priority registers */
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/* mk@tbd: These are the same as beneath for PXA27x: maybe can be
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* merged if GPIO Stuff is same too. */
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/* Missing: 32 Interrupt priority registers
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* These are the same as beneath for PXA27x: maybe can be merged if
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* GPIO Stuff is same too.
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*/
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#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
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#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
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#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
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@ -168,8 +168,6 @@
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#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
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/* nand timeout values */
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#define CFG_NAND_PROG_ERASE_TO 3000
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@ -187,7 +185,6 @@
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#define NAND_TIMING_tRP 40
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#define NAND_TIMING_tR 11123
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/* #define NAND_TIMING_tWHR 110 */
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#define NAND_TIMING_tWHR 100
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#define NAND_TIMING_tAR 10
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@ -208,78 +205,7 @@
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#define NAND_MAX_CHIPS 1
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#define CFG_NO_FLASH 1
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#ifndef CGF_NO_FLASH
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/* these are required by the environment code */
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#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */
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#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */
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#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */
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#endif
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/*
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* GPIO settings
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*/
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#define CFG_GPSR0_VAL 0x00008000
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#define CFG_GPSR1_VAL 0x00FC0382
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#define CFG_GPSR2_VAL 0x0001FFFF
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#define CFG_GPCR0_VAL 0x00000000
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#define CFG_GPCR1_VAL 0x00000000
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#define CFG_GPCR2_VAL 0x00000000
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#define CFG_GPDR0_VAL 0x0060A800
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#define CFG_GPDR1_VAL 0x00FF0382
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#define CFG_GPDR2_VAL 0x0001C000
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#define CFG_GAFR0_L_VAL 0x98400000
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#define CFG_GAFR0_U_VAL 0x00002950
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#define CFG_GAFR1_L_VAL 0x000A9558
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#define CFG_GAFR1_U_VAL 0x0005AAAA
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#define CFG_GAFR2_L_VAL 0xA0000000
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#define CFG_GAFR2_U_VAL 0x00000002
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#define CFG_PSSR_VAL 0x20
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/*
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* Memory settings
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*/
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#define CFG_MSC0_VAL 0x23F223F2
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#define CFG_MSC1_VAL 0x3FF1A441
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#define CFG_MSC2_VAL 0x7FF97FF1
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#define CFG_MDCNFG_VAL 0x00001AC9
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#define CFG_MDREFR_VAL 0x00018018
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#define CFG_MDMRS_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CFG_MECR_VAL 0x00000000
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#define CFG_MCMEM0_VAL 0x00010504
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#define CFG_MCMEM1_VAL 0x00010504
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#define CFG_MCATT0_VAL 0x00010504
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#define CFG_MCATT1_VAL 0x00010504
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#define CFG_MCIO0_VAL 0x00004715
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#define CFG_MCIO1_VAL 0x00004715
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#define _LED 0x08000010
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#define LED_BLANK 0x08000040
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/*
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* FLASH and environment organization
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*/
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#ifndef CFG_NO_FLASH
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
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/* NOTE: many default partitioning schemes assume the kernel starts at the
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* second sector, not an environment. You have been warned!
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*/
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#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
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#endif /* #ifndef CFG_NO_FLASH */
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/* #define CFG_ENV_IS_NOWHERE */
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#define CFG_ENV_IS_IN_NAND 1
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#define CFG_ENV_OFFSET 0x40000
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#define CFG_ENV_OFFSET_REDUND 0x44000
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