mpc83xx: cosmetic: MPC8323ERDB.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
6f681b7349
commit
4dde49d8cb
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@ -68,16 +68,17 @@
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* System performance
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* System performance
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*/
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
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/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
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#define CONFIG_SYS_SPCR_OPT 1
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/*
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/*
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* DDR Setup
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* DDR Setup
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*/
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
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#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
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#undef CONFIG_SPD_EEPROM
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#undef CONFIG_SPD_EEPROM
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#if defined(CONFIG_SPD_EEPROM)
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#if defined(CONFIG_SPD_EEPROM)
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@ -87,51 +88,52 @@
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#else
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#else
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/* Manually set up DDR parameters
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/* Manually set up DDR parameters
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*/
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*/
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#define CONFIG_SYS_DDR_SIZE 64 /* MB */
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#define CONFIG_SYS_DDR_SIZE 64 /* MB */
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#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_WR_ACS \
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| CSCONFIG_ODT_WR_ACS \
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| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_9)
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/* 0x80010101 */
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/* 0x80010101 */
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#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00220802 */
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/* 0x00220802 */
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#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
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#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
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| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
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| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
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| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
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| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
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| (3 << TIMING_CFG1_REFREC_SHIFT) \
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| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
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| (2 << TIMING_CFG1_WRREC_SHIFT) \
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| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x26253222 */
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/* 0x26253222 */
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#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (31 << TIMING_CFG2_CPO_SHIFT ) \
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| (31 << TIMING_CFG2_CPO_SHIFT) \
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| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
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| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
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| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x1f9048c7 */
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/* 0x1f9048c7 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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/* 0x02000000 */
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/* 0x02000000 */
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#define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
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#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
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| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
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| (0x0232 << SDRAM_MODE_SD_SHIFT))
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/* 0x44480232 */
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/* 0x44480232 */
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#define CONFIG_SYS_DDR_MODE2 0x8000c000
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#define CONFIG_SYS_DDR_MODE2 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
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#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
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| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x03200064 */
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/* 0x03200064 */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
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#define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_32_BE )
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| SDRAM_CFG_32_BE)
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/* 0x43080000 */
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/* 0x43080000 */
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#endif
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#endif
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@ -155,16 +157,17 @@
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#endif
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#endif
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/*
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/*
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* Initial RAM Base Address Setup
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* Initial RAM Base Address Setup
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*/
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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/*
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* Local Bus Configuration & Clock Setup
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* Local Bus Configuration & Clock Setup
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@ -178,30 +181,31 @@
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*/
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
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#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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| (2 << BR_PS_SHIFT) /* 16 bit port */ \
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BR_V) /* valid */
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
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#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#undef CONFIG_SYS_FLASH_CHECKSUM
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/*
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/*
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* SDRAM on the Local Bus
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* SDRAM on the Local Bus
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*/
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*/
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#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
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#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
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#ifdef CONFIG_SYS_LB_SDRAM
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#ifdef CONFIG_SYS_LB_SDRAM
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base addr */
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
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* the top 17 bits of BR2.
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* the top 17 bits of BR2.
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*/
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*/
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#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
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/*Port size=32bit, MSEL=SDRAM */
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#define CONFIG_SYS_BR2_PRELIM 0xf0001861
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/*
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/*
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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#define CONFIG_SYS_OR2_PRELIM 0xfc006901
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#define CONFIG_SYS_OR2_PRELIM 0xfc006901
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#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
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/* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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/* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
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#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
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/*
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/*
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* Windows to access PIB via local bus
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* Windows to access PIB via local bus
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*/
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*/
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#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
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/* windows base 0xf8008000 */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
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/*
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/*
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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*/
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#else
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SIZE 0x2000
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/*
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/*
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* Miscellaneous configurable options
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* Miscellaneous configurable options
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*/
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_CMD_KGDB)
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#if (CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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/*
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* For booting Linux, the board info and command line data
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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* the maximum mapped by the Linux kernel during initialization.
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*/
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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/*
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/*
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* Core HID Setup
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* Core HID Setup
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR: cache cacheable */
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/* DDR: cache cacheable */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||||
|
|
||||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
|
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
|
||||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
|
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
|
||||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
| BATL_PP_10 \
|
||||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
|
| BATL_CACHEINHIBIT \
|
||||||
|
| BATL_GUARDEDSTORAGE)
|
||||||
|
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
|
||||||
|
| BATU_BL_4M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||||
|
|
||||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
|
||||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
|
| BATL_PP_10 \
|
||||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
| BATL_MEMCOHERENCE)
|
||||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
|
||||||
|
| BATU_BL_32M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
|
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
|
||||||
|
| BATL_PP_10 \
|
||||||
|
| BATL_CACHEINHIBIT \
|
||||||
|
| BATL_GUARDEDSTORAGE)
|
||||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||||
|
|
||||||
#define CONFIG_SYS_IBAT3L (0)
|
#define CONFIG_SYS_IBAT3L (0)
|
||||||
|
|
@ -467,20 +496,33 @@
|
||||||
|
|
||||||
/* Stack in dcache: cacheable, no memory coherence */
|
/* Stack in dcache: cacheable, no memory coherence */
|
||||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
|
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
|
||||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
|
||||||
|
| BATU_BL_128K \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
||||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
/* PCI MEM space: cacheable */
|
/* PCI MEM space: cacheable */
|
||||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
|
||||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
| BATL_PP_10 \
|
||||||
|
| BATL_MEMCOHERENCE)
|
||||||
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
|
||||||
|
| BATU_BL_256M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
||||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||||
/* PCI MMIO space: cache-inhibit and guarded */
|
/* PCI MMIO space: cache-inhibit and guarded */
|
||||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
|
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
|
||||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
| BATL_PP_10 \
|
||||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
| BATL_CACHEINHIBIT \
|
||||||
|
| BATL_GUARDEDSTORAGE)
|
||||||
|
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
|
||||||
|
| BATU_BL_256M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||||
#else
|
#else
|
||||||
|
|
@ -510,22 +552,26 @@
|
||||||
*/
|
*/
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
|
#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
|
||||||
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
|
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
|
||||||
|
|
||||||
/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
|
/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
|
||||||
#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */
|
* (see CONFIG_SYS_I2C_EEPROM) */
|
||||||
|
/* MAC address offset in I2C EEPROM */
|
||||||
|
#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
|
||||||
|
|
||||||
#define CONFIG_NETDEV eth1
|
#define CONFIG_NETDEV "eth1"
|
||||||
|
|
||||||
#define CONFIG_HOSTNAME mpc8323erdb
|
#define CONFIG_HOSTNAME mpc8323erdb
|
||||||
#define CONFIG_ROOTPATH "/nfsroot"
|
#define CONFIG_ROOTPATH "/nfsroot"
|
||||||
#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
|
|
||||||
#define CONFIG_BOOTFILE "uImage"
|
#define CONFIG_BOOTFILE "uImage"
|
||||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
/* U-Boot image on TFTP server */
|
||||||
#define CONFIG_FDTFILE mpc832x_rdb.dtb
|
#define CONFIG_UBOOTPATH "u-boot.bin"
|
||||||
|
#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
|
||||||
|
#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
|
||||||
|
|
||||||
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
|
/* default location for tftp and bootm */
|
||||||
|
#define CONFIG_LOADADDR 800000
|
||||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
||||||
#define CONFIG_BAUDRATE 115200
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
|
|
@ -533,23 +579,24 @@
|
||||||
#define MK_STR(x) XMK_STR(x)
|
#define MK_STR(x) XMK_STR(x)
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
"netdev=" CONFIG_NETDEV "\0" \
|
||||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
"uboot=" CONFIG_UBOOTPATH "\0" \
|
||||||
"tftpflash=tftp $loadaddr $uboot;" \
|
"tftpflash=tftp $loadaddr $uboot;" \
|
||||||
"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
|
"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
|
||||||
"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
|
"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
|
||||||
"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
|
"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
|
||||||
"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
|
"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
|
||||||
"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
|
"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
|
||||||
"fdtaddr=780000\0" \
|
"fdtaddr=780000\0" \
|
||||||
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
|
"fdtfile=" CONFIG_FDTFILE "\0" \
|
||||||
"ramdiskaddr=1000000\0" \
|
"ramdiskaddr=1000000\0" \
|
||||||
"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
|
"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
|
||||||
"console=ttyS0\0" \
|
"console=ttyS0\0" \
|
||||||
"setbootargs=setenv bootargs " \
|
"setbootargs=setenv bootargs " \
|
||||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
|
||||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
|
||||||
|
"$netdev:off "\
|
||||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
||||||
|
|
||||||
#define CONFIG_NFSBOOTCOMMAND \
|
#define CONFIG_NFSBOOTCOMMAND \
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue