usb: uniphier: remove UniPhier xHCI driver and select DM_USB
This driver has not been converted to Driver Model, and it is an obstacle to migrate other block device drivers. Remove it for now. The UniPhier SoCs already use a DM-based EHCI driver, so now ARCH_UNIPHIER can select DM_USB. These two changes must be done atomically because removing the legacy driver causes a build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Masahiro Yamada
parent
b5550e496e
commit
47a79f657e
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@ -861,6 +861,7 @@ config ARCH_UNIPHIER
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select DM_I2C
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select DM_MMC
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select DM_SERIAL
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select DM_USB
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select OF_CONTROL
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select OF_LIBFDT
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select SPL
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@ -32,7 +32,6 @@ CONFIG_SPL_NAND_DENALI=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_STORAGE=y
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@ -30,7 +30,6 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
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CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
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CONFIG_SPL_NAND_DENALI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_STORAGE=y
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@ -15,13 +15,6 @@ config USB_XHCI_HCD
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if USB_XHCI_HCD
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config USB_XHCI_UNIPHIER
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bool "Support for UniPhier on-chip xHCI USB controller"
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depends on ARCH_UNIPHIER
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default y
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---help---
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Enables support for the on-chip xHCI controller on UniPhier SoCs.
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config USB_XHCI_DWC3
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bool "DesignWare USB3 DRD Core Support"
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help
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@ -62,7 +62,6 @@ obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
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obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
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obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
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obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
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obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
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# designware
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obj-$(CONFIG_USB_DWC2) += dwc2.o
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@ -1,85 +0,0 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <usb.h>
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#include <fdtdec.h>
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#include "xhci.h"
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static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int node_list[2];
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fdt_addr_t addr;
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int count;
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
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COMPAT_SOCIONEXT_XHCI, node_list,
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ARRAY_SIZE(node_list));
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if (index >= count)
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return -ENODEV;
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addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
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if (addr == FDT_ADDR_T_NONE)
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return -ENODEV;
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*base = (struct xhci_hccr *)addr;
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return 0;
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}
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#define USB3_RST_CTRL 0x00100040
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#define IOMMU_RST_N (1 << 5)
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#define LINK_RST_N (1 << 4)
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static void uniphier_xhci_reset(void __iomem *base, int on)
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{
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u32 tmp;
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tmp = readl(base + USB3_RST_CTRL);
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if (on)
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tmp &= ~(IOMMU_RST_N | LINK_RST_N);
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else
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tmp |= IOMMU_RST_N | LINK_RST_N;
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writel(tmp, base + USB3_RST_CTRL);
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}
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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int ret;
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struct xhci_hccr *cr;
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struct xhci_hcor *or;
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ret = get_uniphier_xhci_base(index, &cr);
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if (ret < 0)
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return ret;
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uniphier_xhci_reset(cr, 0);
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or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
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*hccr = cr;
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*hcor = or;
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return 0;
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}
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void xhci_hcd_stop(int index)
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{
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int ret;
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struct xhci_hccr *cr;
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ret = get_uniphier_xhci_base(index, &cr);
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if (ret < 0)
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return;
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uniphier_xhci_reset(cr, 1);
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}
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@ -148,7 +148,6 @@ enum fdt_compat_id {
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COMPAT_INTEL_MICROCODE, /* Intel microcode update */
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COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
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COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
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COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
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COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
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COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
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COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
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@ -59,7 +59,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
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COMPAT(INTEL_MICROCODE, "intel,microcode"),
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COMPAT(AMS_AS3722, "ams,as3722"),
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COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
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COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
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COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
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COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
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COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
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