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nds32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment 

Add ARCH_DMA_MINALIGN definition to asm/cache.h

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
This commit is contained in:
Macpaul Lin 2011-10-24 16:48:39 +08:00
parent 569bc625e3
commit 466e73b19b
1 changed files with 11 additions and 0 deletions
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11
arch/nds32/include/asm/cache.h
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@ -51,4 +51,15 @@ DEFINE_GET_SYS_REG(DCM_CFG);
#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */
#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
/*
* The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
* We use that value for aligning DMA buffers unless the board config has
* specified an alternate cache line size.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 32
#endif
#endif /* _ASM_CACHE_H */