exynos: i2c: Tidy up the driver model code
The existing driver model implementation uses the old non-driver-model code to operate, but has become impossibly tangled as a result. The actual algorithm is quite simple. Also the normal-speed and high-speed buses are quite different and it doesn't seem that useful to put them in the same driver. Finally, there is a bug which breaks communication with the Maxim sound codec and may cause problems with other device. Rewrite the driver model code for normal-speed operation so that it is easier to understand, and fix the bug. Add a TODO to split the drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
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Simon Glass
parent
26ea76850e
commit
45d9ae87cb
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@ -1284,62 +1284,106 @@ U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
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#endif /* CONFIG_SYS_I2C */
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#ifdef CONFIG_DM_I2C
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static int i2c_write_data(struct s3c24x0_i2c_bus *i2c_bus, uchar chip,
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uchar *buffer, int len, bool end_with_repeated_start)
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static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
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struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
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int ret;
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if (i2c_bus->is_highspeed) {
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ret = hsi2c_write(i2c_bus->hsregs, chip, 0, 0,
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buffer, len, true);
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if (ret)
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for (; nmsgs > 0; nmsgs--, msg++) {
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if (msg->flags & I2C_M_RD) {
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ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
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msg->len);
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} else {
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ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
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msg->len, true);
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}
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if (ret) {
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exynos5_i2c_reset(i2c_bus);
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} else {
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ret = i2c_transfer(i2c_bus->regs, I2C_WRITE,
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chip << 1, 0, 0, buffer, len);
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return -EREMOTEIO;
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}
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}
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return ret != I2C_OK;
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return 0;
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}
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static int i2c_read_data(struct s3c24x0_i2c_bus *i2c_bus, uchar chip,
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uchar *buffer, int len)
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static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
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int seq)
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{
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int ret;
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struct s3c24x0_i2c *i2c = i2c_bus->regs;
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bool is_read = msg->flags & I2C_M_RD;
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uint status;
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uint addr;
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int ret, i;
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if (i2c_bus->is_highspeed) {
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ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buffer, len);
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if (ret)
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exynos5_i2c_reset(i2c_bus);
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if (!seq)
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setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
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/* Get the slave chip address going */
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addr = msg->addr << 1;
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writel(addr, &i2c->iicds);
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status = I2C_TXRX_ENA | I2C_START_STOP;
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if (is_read)
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status |= I2C_MODE_MR;
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else
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status |= I2C_MODE_MT;
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writel(status, &i2c->iicstat);
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if (seq)
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read_write_byte(i2c);
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/* Wait for chip address to transmit */
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ret = WaitForXfer(i2c);
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if (ret)
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goto err;
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if (is_read) {
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for (i = 0; !ret && i < msg->len; i++) {
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/* disable ACK for final READ */
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if (i == msg->len - 1)
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clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
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read_write_byte(i2c);
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ret = WaitForXfer(i2c);
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msg->buf[i] = readl(&i2c->iicds);
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}
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if (ret == I2C_NACK)
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ret = I2C_OK; /* Normal terminated read */
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} else {
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ret = i2c_transfer(i2c_bus->regs, I2C_READ,
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chip << 1, 0, 0, buffer, len);
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for (i = 0; !ret && i < msg->len; i++) {
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writel(msg->buf[i], &i2c->iicds);
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read_write_byte(i2c);
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ret = WaitForXfer(i2c);
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}
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}
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return ret != I2C_OK;
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err:
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return ret;
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}
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static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
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int ret;
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struct s3c24x0_i2c *i2c = i2c_bus->regs;
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ulong start_time;
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int ret, i;
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for (; nmsgs > 0; nmsgs--, msg++) {
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bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
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if (msg->flags & I2C_M_RD) {
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ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
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msg->len);
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} else {
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ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
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msg->len, next_is_read);
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start_time = get_timer(0);
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while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
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if (get_timer(start_time) > I2C_TIMEOUT_MS) {
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debug("Timeout\n");
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return -ETIMEDOUT;
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}
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if (ret)
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return -EREMOTEIO;
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}
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return 0;
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for (ret = 0, i = 0; !ret && i < nmsgs; i++)
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ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
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/* Send STOP */
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writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
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read_write_byte(i2c);
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return ret ? -EREMOTEIO : 0;
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}
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static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
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@ -1364,8 +1408,7 @@ static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
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i2c_bus->id = pinmux_decode_periph_id(blob, node);
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i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
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"clock-frequency",
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CONFIG_SYS_I2C_S3C24X0_SPEED);
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"clock-frequency", 100000);
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i2c_bus->node = node;
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i2c_bus->bus_num = dev->seq;
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@ -1384,7 +1427,6 @@ static const struct dm_i2c_ops s3c_i2c_ops = {
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static const struct udevice_id s3c_i2c_ids[] = {
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{ .compatible = "samsung,s3c2440-i2c", .data = EXYNOS_I2C_STD },
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{ .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS },
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{ }
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};
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@ -1397,4 +1439,29 @@ U_BOOT_DRIVER(i2c_s3c) = {
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.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
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.ops = &s3c_i2c_ops,
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};
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/*
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* TODO(sjg@chromium.org): Move this to a separate file when everything uses
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* driver model
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*/
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static const struct dm_i2c_ops exynos_hs_i2c_ops = {
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.xfer = exynos_hs_i2c_xfer,
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.probe_chip = s3c24x0_i2c_probe,
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.set_bus_speed = s3c24x0_i2c_set_bus_speed,
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};
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static const struct udevice_id exynos_hs_i2c_ids[] = {
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{ .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS },
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{ }
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};
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U_BOOT_DRIVER(hs_i2c) = {
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.name = "i2c_s3c_hs",
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.id = UCLASS_I2C,
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.of_match = exynos_hs_i2c_ids,
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.ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
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.per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
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.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
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.ops = &exynos_hs_i2c_ops,
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};
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#endif /* CONFIG_DM_I2C */
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