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Adjust configuration of XENIAX board 

(chip select and GPIO required for USB operation)
This commit is contained in:
Wolfgang Denk 2005-08-04 19:45:01 +02:00
parent 3e0bc4473a
commit 452f67407b
2 changed files with 6 additions and 3 deletions
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3
CHANGELOG
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@ -2,6 +2,9 @@
Changes for U-Boot 1.1.3: Changes for U-Boot 1.1.3:
====================================================================== ======================================================================
* Adjust configuration of XENIAX board
(chip select and GPIO required for USB operation)
* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be * Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
routed to the Watchdog handler routed to the Watchdog handler
Patch by Eugene Surovegin, 18 Jun 2005 Patch by Eugene Surovegin, 18 Jun 2005

6
include/configs/xaeniax.h
View File

@ -236,7 +236,7 @@
* GP30 == SDATA_OUT is 0 * GP30 == SDATA_OUT is 0
* GP81 == NSSPCLK is 0 * GP81 == NSSPCLK is 0
*/ */
#define CFG_GPCR0_VAL 0x40C31868 #define CFG_GPCR0_VAL 0x40C31848
#define CFG_GPCR1_VAL 0x00000000 #define CFG_GPCR1_VAL 0x00000000
#define CFG_GPCR2_VAL 0x00020000 #define CFG_GPCR2_VAL 0x00020000
@ -455,10 +455,10 @@
* [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
* [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
* [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
* [03] 0 - 32 Bit bus width * [03] 1 - 16 Bit bus width
* [02:00] 100 - variable latency I/O * [02:00] 100 - variable latency I/O
*/ */
#define CFG_MSC1_VAL 0x1224A264 #define CFG_MSC1_VAL 0x1224A26C
/* This is the configuration for nCS4/5 -> LAN /* This is the configuration for nCS4/5 -> LAN
* configuration for nCS5: * configuration for nCS5: