imx:mx6ul add clock support
1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
436cf40f05
commit
43cb127b75
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@ -81,19 +81,32 @@ void enable_usboh3_clk(unsigned char enable)
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#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
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void enable_enet_clk(unsigned char enable)
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{
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u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
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u32 mask, *addr;
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if (is_cpu_type(MXC_CPU_MX6UL)) {
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mask = MXC_CCM_CCGR3_ENET_MASK;
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addr = &imx_ccm->CCGR3;
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} else {
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mask = MXC_CCM_CCGR1_ENET_MASK;
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addr = &imx_ccm->CCGR1;
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}
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if (enable)
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setbits_le32(&imx_ccm->CCGR1, mask);
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setbits_le32(addr, mask);
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else
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clrbits_le32(&imx_ccm->CCGR1, mask);
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clrbits_le32(addr, mask);
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}
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#endif
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#ifdef CONFIG_MXC_UART
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void enable_uart_clk(unsigned char enable)
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{
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u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
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u32 mask;
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if (is_cpu_type(MXC_CPU_MX6UL))
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mask = MXC_CCM_CCGR5_UART_MASK;
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else
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mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
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if (enable)
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setbits_le32(&imx_ccm->CCGR5, mask);
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@ -141,7 +154,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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reg &= ~mask;
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__raw_writel(reg, &imx_ccm->CCGR2);
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} else {
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if (is_cpu_type(MXC_CPU_MX6SX)) {
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if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
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mask = MXC_CCM_CCGR6_I2C4_MASK;
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addr = &imx_ccm->CCGR6;
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} else {
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@ -214,9 +227,11 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
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switch (pll) {
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case PLL_BUS:
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if (pfd_num == 3) {
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/* No PFD3 on PPL2 */
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return 0;
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if (!is_cpu_type(MXC_CPU_MX6UL)) {
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if (pfd_num == 3) {
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/* No PFD3 on PPL2 */
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return 0;
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}
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}
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div = __raw_readl(&imx_ccm->analog_pfd_528);
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freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
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@ -248,10 +263,12 @@ static u32 get_mcu_main_clk(void)
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u32 get_periph_clk(void)
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{
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u32 reg, freq = 0;
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u32 reg, div = 0, freq = 0;
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reg = __raw_readl(&imx_ccm->cbcdr);
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if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
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div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
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MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
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reg = __raw_readl(&imx_ccm->cbcmr);
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reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
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reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
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@ -291,7 +308,7 @@ u32 get_periph_clk(void)
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}
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}
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return freq;
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return freq / (div + 1);
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}
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static u32 get_ipg_clk(void)
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@ -311,7 +328,7 @@ static u32 get_ipg_per_clk(void)
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reg = __raw_readl(&imx_ccm->cscmr1);
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if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
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is_mx6dqp()) {
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is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
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if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
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return MXC_HCLK; /* OSC 24Mhz */
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}
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@ -328,7 +345,7 @@ static u32 get_uart_clk(void)
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reg = __raw_readl(&imx_ccm->cscdr1);
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if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
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is_mx6dqp()) {
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is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
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if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
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freq = MXC_HCLK;
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}
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@ -347,7 +364,8 @@ static u32 get_cspi_clk(void)
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cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
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MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
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if (is_mx6dqp()) {
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if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
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is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
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if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
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return MXC_HCLK / (cspi_podf + 1);
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}
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@ -402,47 +420,60 @@ static u32 get_emi_slow_clk(void)
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return root_freq / (emi_slow_podf + 1);
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}
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#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
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static u32 get_mmdc_ch0_clk(void)
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{
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u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
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u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
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u32 freq, podf;
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podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
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>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
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u32 freq, podf, per2_clk2_podf;
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switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
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MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
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case 0:
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freq = decode_pll(PLL_BUS, MXC_HCLK);
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break;
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case 1:
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freq = mxc_get_pll_pfd(PLL_BUS, 2);
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break;
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case 2:
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freq = mxc_get_pll_pfd(PLL_BUS, 0);
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break;
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case 3:
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/* static / 2 divider */
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freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
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if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
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is_cpu_type(MXC_CPU_MX6SL)) {
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podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
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MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
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if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
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per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
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MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
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if (is_cpu_type(MXC_CPU_MX6SL)) {
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if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
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freq = MXC_HCLK;
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else
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freq = decode_pll(PLL_USBOTG, MXC_HCLK);
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} else {
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if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
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freq = decode_pll(PLL_BUS, MXC_HCLK);
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else
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freq = decode_pll(PLL_USBOTG, MXC_HCLK);
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}
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} else {
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per2_clk2_podf = 0;
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switch ((cbcmr &
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MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
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MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
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case 0:
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freq = decode_pll(PLL_BUS, MXC_HCLK);
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break;
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case 1:
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freq = mxc_get_pll_pfd(PLL_BUS, 2);
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break;
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case 2:
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freq = mxc_get_pll_pfd(PLL_BUS, 0);
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break;
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case 3:
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/* static / 2 divider */
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freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
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break;
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}
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}
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return freq / (podf + 1) / (per2_clk2_podf + 1);
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} else {
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podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
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MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
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return get_periph_clk() / (podf + 1);
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}
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return freq / (podf + 1);
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}
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#else
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static u32 get_mmdc_ch0_clk(void)
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{
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u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
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u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
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MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
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return get_periph_clk() / (mmdc_ch0_podf + 1);
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}
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#endif
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#ifdef CONFIG_MX6SX
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#ifdef CONFIG_FSL_QSPI
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/* qspi_num can be from 0 - 1 */
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void enable_qspi_clk(int qspi_num)
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{
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@ -603,6 +634,7 @@ u32 imx_get_fecclk(void)
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return mxc_get_clock(MXC_IPG_CLK);
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}
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#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
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static int enable_enet_pll(uint32_t en)
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{
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struct mxc_ccm_reg *const imx_ccm
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@ -627,8 +659,9 @@ static int enable_enet_pll(uint32_t en)
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writel(reg, &imx_ccm->analog_pll_enet);
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return 0;
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}
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#endif
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#ifndef CONFIG_MX6SX
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#ifdef CONFIG_CMD_SATA
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static void ungate_sata_clock(void)
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{
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struct mxc_ccm_reg *const imx_ccm =
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@ -637,18 +670,7 @@ static void ungate_sata_clock(void)
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/* Enable SATA clock. */
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setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
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}
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#endif
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static void ungate_pcie_clock(void)
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{
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struct mxc_ccm_reg *const imx_ccm =
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(struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* Enable PCIe clock. */
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setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
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}
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#ifndef CONFIG_MX6SX
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int enable_sata_clock(void)
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{
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ungate_sata_clock();
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@ -664,6 +686,16 @@ void disable_sata_clock(void)
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}
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#endif
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#ifdef CONFIG_PCIE_IMX
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static void ungate_pcie_clock(void)
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{
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struct mxc_ccm_reg *const imx_ccm =
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(struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* Enable PCIe clock. */
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setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
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}
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int enable_pcie_clock(void)
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{
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struct anatop_regs *anatop_regs =
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@ -703,7 +735,7 @@ int enable_pcie_clock(void)
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clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
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/* Party time! Ungate the clock to the PCIe. */
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#ifndef CONFIG_MX6SX
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#ifdef CONFIG_CMD_SATA
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ungate_sata_clock();
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#endif
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ungate_pcie_clock();
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@ -711,6 +743,7 @@ int enable_pcie_clock(void)
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return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
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BM_ANADIG_PLL_ENET_ENABLE_PCIE);
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}
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#endif
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#ifdef CONFIG_SECURE_BOOT
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void hab_caam_clock_enable(unsigned char enable)
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@ -110,6 +110,7 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCR_RBC_EN (1 << 27)
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#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
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#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
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/* CCR_WB does not exist on i.MX6SX/UL */
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#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
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#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
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#define MXC_CCM_CCR_COSC_EN (1 << 12)
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@ -150,12 +151,11 @@ struct mxc_ccm_reg {
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/* Define the bits in register CBCDR */
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#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
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#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
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#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
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#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
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#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
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#ifndef CONFIG_MX6SX
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/* MMDC_CH0 not exists on i.MX6SX */
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#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
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#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
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#endif
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#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
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#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
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#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
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@ -178,7 +178,7 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
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#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
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#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
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#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
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#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
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#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
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#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
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#ifndef CONFIG_MX6SX
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@ -203,18 +203,19 @@ struct mxc_ccm_reg {
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/* Define the bits in register CSCMR1 */
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#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
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#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
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#ifdef CONFIG_MX6SX
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/* QSPI1 exist on i.MX6SX/UL */
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#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
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#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
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#else
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#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
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#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
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#endif
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#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
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#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
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/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
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#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
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#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
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/* CSCMR1_GPMI/BCH exist on i.MX6UL */
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#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
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#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
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#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
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#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
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#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
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@ -225,10 +226,9 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
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#ifdef CONFIG_MX6SX
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/* QSPI1 exist on i.MX6SX/UL */
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#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
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#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
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#endif
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/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
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#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
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#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
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@ -256,6 +256,12 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
|
||||
#endif
|
||||
/* CSCDR1_GPMI/BCH exist on i.MX6UL */
|
||||
#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
|
||||
#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
|
||||
|
||||
#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
|
||||
#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
|
||||
|
|
@ -290,7 +296,7 @@ struct mxc_ccm_reg {
|
|||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CS2CDR */
|
||||
#ifdef CONFIG_MX6SX
|
||||
/* QSPI2 on i.MX6SX */
|
||||
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
|
||||
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
|
||||
|
|
@ -300,7 +306,7 @@ struct mxc_ccm_reg {
|
|||
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
|
||||
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
|
||||
#else
|
||||
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
|
||||
|
|
@ -308,14 +314,26 @@ struct mxc_ccm_reg {
|
|||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
|
||||
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
|
||||
(is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
|
||||
(is_mx6dqp() ? 15 : 16)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
|
||||
(is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
|
||||
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
|
||||
((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
|
||||
((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
|
||||
((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
|
||||
|
||||
#endif
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
|
||||
|
|
@ -543,10 +561,9 @@ struct mxc_ccm_reg {
|
|||
#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
|
||||
#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
|
||||
#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
|
||||
#ifndef CONFIG_MX6SX
|
||||
#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
|
||||
#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
|
||||
#endif
|
||||
/* CCGR1_ENET does not exist on i.MX6SX/UL */
|
||||
#define MXC_CCM_CCGR1_ENET_OFFSET 10
|
||||
#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
|
||||
#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
|
||||
#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
|
||||
#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
|
||||
|
|
@ -617,21 +634,21 @@ struct mxc_ccm_reg {
|
|||
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MX6SX
|
||||
/* Exist on i.MX6SX */
|
||||
#define MXC_CCM_CCGR3_M4_OFFSET 2
|
||||
#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
|
||||
#define MXC_CCM_CCGR3_ENET_OFFSET 4
|
||||
#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
|
||||
#define MXC_CCM_CCGR3_QSPI_OFFSET 14
|
||||
#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
|
||||
#else
|
||||
|
||||
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
|
||||
#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
|
||||
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
|
||||
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
|
||||
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
|
||||
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
|
||||
#endif
|
||||
|
||||
#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
|
||||
#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
|
||||
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
|
||||
|
|
@ -640,15 +657,22 @@ struct mxc_ccm_reg {
|
|||
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
|
||||
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
|
||||
#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
|
||||
#ifdef CONFIG_MX6SX
|
||||
|
||||
/* QSPI1 exists on i.MX6SX/UL */
|
||||
#define MXC_CCM_CCGR3_QSPI1_OFFSET 14
|
||||
#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
|
||||
#else
|
||||
|
||||
#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
|
||||
#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
|
||||
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
|
||||
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
|
||||
#endif
|
||||
|
||||
/* A7_CLKDIV/WDOG1 on i.MX6UL */
|
||||
#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
|
||||
#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
|
||||
#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
|
||||
#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
|
||||
|
||||
#define MXC_CCM_CCGR3_MLB_OFFSET 18
|
||||
#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
|
||||
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
|
||||
|
|
@ -661,8 +685,16 @@ struct mxc_ccm_reg {
|
|||
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
|
||||
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
|
||||
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
|
||||
/* AXI on i.MX6UL */
|
||||
#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
|
||||
#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
|
||||
#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
|
||||
#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
|
||||
|
||||
/* GPIO4 on i.MX6UL */
|
||||
#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
|
||||
#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
|
||||
|
||||
#ifndef CONFIG_MX6SX
|
||||
#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
|
||||
#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
|
||||
|
|
@ -670,13 +702,11 @@ struct mxc_ccm_reg {
|
|||
|
||||
#define MXC_CCM_CCGR4_PCIE_OFFSET 0
|
||||
#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
|
||||
#ifdef CONFIG_MX6SX
|
||||
/* QSPI2 on i.MX6SX */
|
||||
#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
|
||||
#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
|
||||
#else
|
||||
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
|
||||
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
|
||||
#endif
|
||||
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
|
||||
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
|
||||
#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
|
||||
|
|
@ -736,6 +766,12 @@ struct mxc_ccm_reg {
|
|||
#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
|
||||
#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
|
||||
#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
|
||||
/* GPMI/BCH on i.MX6UL */
|
||||
#define MXC_CCM_CCGR6_BCH_OFFSET 6
|
||||
#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
|
||||
#define MXC_CCM_CCGR6_GPMI_OFFSET 8
|
||||
#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
|
||||
|
||||
#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
|
||||
#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
|
||||
#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
|
||||
|
|
|
|||
Loading…
Reference in New Issue