ARM: omap: move board specific NAND configs out from ti_armv7_common.h
This patch moves some board specific NAND configs: - FROM: generic config file 'ti_armv7_common.h' - TO: individual board config files using these configs. So that each board can independently set the value as per its design. Following configs are affected in this patch: CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand> CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon> CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon> CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon> This patch also updates documentation for few of above NAND configs. Signed-off-by: Pekon Gupta <pekon@ti.com>
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@ -89,6 +89,10 @@ Commands:
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Configuration Options:
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CONFIG_SYS_NAND_U_BOOT_OFFS
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NAND Offset from where SPL will read u-boot image. This is the starting
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address of u-boot MTD partition in NAND.
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CONFIG_CMD_NAND
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Enables NAND support and commmands.
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@ -226,6 +230,14 @@ Platform specific options
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detection. However ECC calculation on such plaforms would still be
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done by GPMC controller.
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CONFIG_SPL_NAND_AM33XX_BCH
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Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
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hardware ECC correction. This is useful for platforms which have ELM
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hardware engine and use NAND boot mode.
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Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
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so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
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SPL-NAND driver with software ECC correction support.
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CONFIG_NAND_OMAP_ECCSCHEME
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On OMAP platforms, this CONFIG specifies NAND ECC scheme.
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It can take following values:
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@ -254,6 +254,11 @@
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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#endif
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#endif
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@ -150,6 +150,11 @@
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#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x400000 /* un-assigned: (using dtb) */
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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/* GPIO pin + bank to pin ID mapping */
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#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
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@ -303,5 +303,11 @@
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x240000
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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#endif /* __CONFIG_H */
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@ -196,6 +196,13 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x240000
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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#endif
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#endif /* __IGEP00X0_H */
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@ -216,5 +216,11 @@
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x240000
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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#endif /* __CONFIG_H */
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@ -70,6 +70,12 @@
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"4m(kernel),-(fs)"
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#if defined(CONFIG_CMD_NAND)
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x240000
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
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#endif
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@ -159,6 +159,12 @@
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* un-assigned */
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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/*
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* USB configuration. We enable MUSB support, both for host and for
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@ -243,13 +243,6 @@
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#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
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#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
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/* NAND */
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#ifdef CONFIG_NAND
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#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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/* spl export command */
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#define CONFIG_CMD_SPL
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#endif
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@ -275,7 +268,6 @@
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_MTD_SUPPORT
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif
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#endif /* !CONFIG_NOR_BOOT */
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