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arm: zynq: Move serial driver to driver model 

Update this driver to use driver model and change all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Simon Glass 2015-10-17 19:41:27 -06:00 committed by Michal Simek
parent 325c8d569e
commit 42800ffa79
10 changed files with 72 additions and 118 deletions

1
arch/arm/Kconfig
View File

@ -547,6 +547,7 @@ config ARCH_ZYNQ
select DM
select SPL_DM
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
select SPL_SEPARATE_BSS

173
drivers/serial/serial_zynq.c
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@ -6,6 +6,8 @@
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <watchdog.h>
@ -18,6 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
@ -38,9 +41,8 @@ struct uart_zynq {
u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
};
static struct uart_zynq *uart_zynq_ports[2] = {
[0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
[1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
struct zynq_uart_priv {
struct uart_zynq *regs;
};
/* Set up the baud rate in gd struct */
@ -84,15 +86,6 @@ static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
writel(bgen, &regs->baud_rate_gen);
}
/* Set up the baud rate in gd struct */
static void uart_zynq_serial_setbrg(const int port)
{
unsigned long clock = get_uart_clk(port);
struct uart_zynq *regs = uart_zynq_ports[port];
return _uart_zynq_serial_setbrg(regs, clock, gd->baudrate);
}
/* Initialize the UART, with...some settings. */
static void _uart_zynq_serial_init(struct uart_zynq *regs)
{
@ -102,20 +95,6 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs)
writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
}
/* Initialize the UART, with...some settings. */
static int uart_zynq_serial_init(const int port)
{
struct uart_zynq *regs = uart_zynq_ports[port];
if (!regs)
return -1;
_uart_zynq_serial_init(regs);
uart_zynq_serial_setbrg(port);
return 0;
}
static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
@ -126,104 +105,92 @@ static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
return 0;
}
static void uart_zynq_serial_putc(const char c, const int port)
int zynq_serial_setbrg(struct udevice *dev, int baudrate)
{
struct uart_zynq *regs = uart_zynq_ports[port];
struct zynq_uart_priv *priv = dev_get_priv(dev);
unsigned long clock = get_uart_clk(0);
while (_uart_zynq_serial_putc(regs, c) == -EAGAIN)
WATCHDOG_RESET();
_uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
if (c == '\n') {
while (_uart_zynq_serial_putc(regs, '\r') == -EAGAIN)
WATCHDOG_RESET();
}
return 0;
}
static void uart_zynq_serial_puts(const char *s, const int port)
static int zynq_serial_probe(struct udevice *dev)
{
while (*s)
uart_zynq_serial_putc(*s++, port);
struct zynq_uart_priv *priv = dev_get_priv(dev);
_uart_zynq_serial_init(priv->regs);
return 0;
}
static int uart_zynq_serial_tstc(const int port)
static int zynq_serial_getc(struct udevice *dev)
{
struct uart_zynq *regs = uart_zynq_ports[port];
struct zynq_uart_priv *priv = dev_get_priv(dev);
struct uart_zynq *regs = priv->regs;
return (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
}
if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
return -EAGAIN;
static int uart_zynq_serial_getc(const int port)
{
struct uart_zynq *regs = uart_zynq_ports[port];
while (!uart_zynq_serial_tstc(port))
WATCHDOG_RESET();
return readl(&regs->tx_rx_fifo);
}
/* Multi serial device functions */
#define DECLARE_PSSERIAL_FUNCTIONS(port) \
static int uart_zynq##port##_init(void) \
{ return uart_zynq_serial_init(port); } \
static void uart_zynq##port##_setbrg(void) \
{ return uart_zynq_serial_setbrg(port); } \
static int uart_zynq##port##_getc(void) \
{ return uart_zynq_serial_getc(port); } \
static int uart_zynq##port##_tstc(void) \
{ return uart_zynq_serial_tstc(port); } \
static void uart_zynq##port##_putc(const char c) \
{ uart_zynq_serial_putc(c, port); } \
static void uart_zynq##port##_puts(const char *s) \
{ uart_zynq_serial_puts(s, port); }
/* Serial device descriptor */
#define INIT_PSSERIAL_STRUCTURE(port, __name) { \
.name = __name, \
.start = uart_zynq##port##_init, \
.stop = NULL, \
.setbrg = uart_zynq##port##_setbrg, \
.getc = uart_zynq##port##_getc, \
.tstc = uart_zynq##port##_tstc, \
.putc = uart_zynq##port##_putc, \
.puts = uart_zynq##port##_puts, \
}
DECLARE_PSSERIAL_FUNCTIONS(0);
static struct serial_device uart_zynq_serial0_device =
INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
DECLARE_PSSERIAL_FUNCTIONS(1);
static struct serial_device uart_zynq_serial1_device =
INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
__weak struct serial_device *default_serial_console(void)
static int zynq_serial_putc(struct udevice *dev, const char ch)
{
const void *blob = gd->fdt_blob;
int node;
unsigned int base_addr;
struct zynq_uart_priv *priv = dev_get_priv(dev);
node = fdt_path_offset(blob, "serial0");
if (node < 0)
return NULL;
base_addr = fdtdec_get_addr(blob, node, "reg");
if (base_addr == FDT_ADDR_T_NONE)
return NULL;
if (base_addr == ZYNQ_SERIAL_BASEADDR0)
return &uart_zynq_serial0_device;
if (base_addr == ZYNQ_SERIAL_BASEADDR1)
return &uart_zynq_serial1_device;
return NULL;
return _uart_zynq_serial_putc(priv->regs, ch);
}
void zynq_serial_initialize(void)
static int zynq_serial_pending(struct udevice *dev, bool input)
{
serial_register(&uart_zynq_serial0_device);
serial_register(&uart_zynq_serial1_device);
struct zynq_uart_priv *priv = dev_get_priv(dev);
struct uart_zynq *regs = priv->regs;
if (input)
return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
else
return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
}
static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
{
struct zynq_uart_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (struct uart_zynq *)addr;
return 0;
}
static const struct dm_serial_ops zynq_serial_ops = {
.putc = zynq_serial_putc,
.pending = zynq_serial_pending,
.getc = zynq_serial_getc,
.setbrg = zynq_serial_setbrg,
};
static const struct udevice_id zynq_serial_ids[] = {
{ .compatible = "xlnx,xuartps" },
{ .compatible = "cdns,uart-r1p8" },
{ }
};
U_BOOT_DRIVER(serial_s5p) = {
.name = "serial_zynq",
.id = UCLASS_SERIAL,
.of_match = zynq_serial_ids,
.ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct zynq_uart_priv),
.probe = zynq_serial_probe,
.ops = &zynq_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#ifdef CONFIG_DEBUG_UART_ZYNQ
#include <debug_uart.h>

4
include/configs/xilinx_zynqmp.h
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@ -55,9 +55,7 @@
# define CONFIG_ARM_DCC
# define CONFIG_CPU_ARMV8
#else
# if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
# define CONFIG_ZYNQ_SERIAL
# endif
# define CONFIG_ZYNQ_SERIAL
#endif
#define CONFIG_CONS_INDEX 0

1
include/configs/xilinx_zynqmp_ep.h
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@ -18,7 +18,6 @@
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
#define CONFIG_ZYNQ_SERIAL_UART0
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_I2C0
#define CONFIG_SYS_I2C_ZYNQ

1
include/configs/zynq_microzed.h
View File

@ -12,7 +12,6 @@
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0

1
include/configs/zynq_picozed.h
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@ -12,7 +12,6 @@
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0

1
include/configs/zynq_zc70x.h
View File

@ -12,7 +12,6 @@
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7

6
include/configs/zynq_zc770.h
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@ -15,26 +15,20 @@
#define CONFIG_SYS_NO_FLASH
#if defined(CONFIG_ZC770_XM010)
# define CONFIG_ZYNQ_SERIAL_UART1
# define CONFIG_ZYNQ_GEM0
# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
# define CONFIG_ZYNQ_SDHCI0
# define CONFIG_ZYNQ_SPI
#elif defined(CONFIG_ZC770_XM011)
# define CONFIG_ZYNQ_SERIAL_UART1
#elif defined(CONFIG_ZC770_XM012)
# define CONFIG_ZYNQ_SERIAL_UART1
# undef CONFIG_SYS_NO_FLASH
#elif defined(CONFIG_ZC770_XM013)
# define CONFIG_ZYNQ_SERIAL_UART0
# define CONFIG_ZYNQ_GEM1
# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7
#else
# define CONFIG_ZYNQ_SERIAL_UART0
#endif
#include <configs/zynq-common.h>

1
include/configs/zynq_zed.h
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@ -12,7 +12,6 @@
#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0

1
include/configs/zynq_zybo.h
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@ -13,7 +13,6 @@
#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0