ARM: atmel: at91sam9m10g45ek: enable spl support
Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system. As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM. Signed-off-by: Bo Shen <voice.shen@atmel.com>
This commit is contained in:
Bo Shen
Andreas Bießmann
parent
72cb3b6b54
commit
41d41a93fb
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@ -66,6 +66,7 @@ config TARGET_STAMP9G20
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config TARGET_AT91SAM9M10G45EK
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bool "Atmel AT91SAM9M10G45-EK board"
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select CPU_ARM926EJS
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select SUPPORT_SPL
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config TARGET_PM9G45
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bool "Ronetix pm9g45 board"
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@ -0,0 +1,48 @@
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/*
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* Copyright (C) 2015 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
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LENGTH = CONFIG_SPL_MAX_SIZE }
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MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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.text :
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{
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__start = .;
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*(.vectors)
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arch/arm/cpu/arm926ejs/start.o (.text*)
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*(.text*)
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} >.sram
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
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. = ALIGN(4);
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
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. = ALIGN(4);
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__image_copy_end = .;
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.end :
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{
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*(.__end)
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} >.sram
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.bss :
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{
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. = ALIGN(4);
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__bss_start = .;
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*(.bss*)
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. = ALIGN(4);
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__bss_end = .;
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} >.sdram
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}
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@ -71,7 +71,11 @@ void __weak at91_spl_board_init(void)
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{
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}
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void spl_board_init(void)
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void __weak spl_board_init(void)
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{
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}
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void board_init_f(ulong dummy)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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@ -8,6 +8,7 @@
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/at91sam9g45_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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@ -15,6 +16,7 @@
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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#include <linux/mtd/nand.h>
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#include <atmel_lcdc.h>
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#include <atmel_mci.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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@ -71,6 +73,84 @@ void at91sam9m10g45ek_nand_hw_init(void)
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}
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#endif
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#if defined(CONFIG_SPL_BUILD)
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#include <spl.h>
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#include <nand.h>
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void at91_spl_board_init(void)
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{
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/*
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* On the at91sam9m10g45ek board, the chip wm9711 stays in the
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* test mode, so it needs do some action to exit test mode.
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*/
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at91_periph_clk_enable(ATMEL_ID_PIODE);
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at91_set_gpio_output(AT91_PIN_PD7, 0);
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at91_set_gpio_output(AT91_PIN_PD8, 0);
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at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
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at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
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#ifdef CONFIG_SYS_USE_MMC
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at91_mci_hw_init();
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#elif CONFIG_SYS_USE_NANDFLASH
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at91sam9m10g45ek_nand_hw_init();
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#endif
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}
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#include <asm/arch/atmel_mpddrc.h>
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static void ddr2_conf(struct atmel_mpddr *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_DQMS_SHARED |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
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ddr2->rtr = 0x24b;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
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1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
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1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct atmel_mpddr ddr2;
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unsigned long csa;
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(0x4, &pmc->scer);
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/* Chip select 1 is for DDR2/SDRAM */
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csa = readl(&mat->ebicsa);
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csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
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csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
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writel(csa, &mat->ebicsa);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_CS6, &ddr2);
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}
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#endif
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#ifdef CONFIG_CMD_USB
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static void at91sam9m10g45ek_usb_hw_init(void)
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{
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@ -1,3 +1,4 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
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CONFIG_ARM=y
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CONFIG_ARCH_AT91=y
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@ -1,3 +1,4 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
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CONFIG_ARM=y
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CONFIG_ARCH_AT91=y
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@ -203,4 +203,62 @@
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x010000
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#define CONFIG_SPL_STACK 0x310000
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_BSS_START_ADDR 0x70000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
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#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#elif CONFIG_SYS_USE_NANDFLASH
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, }
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#endif
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#define CONFIG_SPL_ATMEL_SIZE
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define CONFIG_SYS_AT91_PLLA 0x20c73f03
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
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#endif
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