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ARM: OMAP4470: Add voltage and dpll data 

OMAP4470 reference design uses TWL6032 PMIC
with a following connection scheme:
  VDD_CORE = TWL6032 SMPS2
  VDD_MPU  = TWL6032 SMPS1
  VDD_IVA  = TWL6032 SMPS5

Set voltage and frequency values according to
OMAP4470 Data Manual Operating Condition Addendum v0.7

Signed-off-by: Taras Kondratiuk <taras@ti.com>
This commit is contained in:
Taras Kondratiuk 2013-08-06 15:18:49 +03:00 committed by Tom Rini
parent 696f81f9a9
commit 40aadf9201
2 changed files with 42 additions and 1 deletions
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36
arch/arm/cpu/armv7/omap4/hw_data.c
View File

@ -50,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
/*
* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
* OMAP4430 OPP_TURBO frequency
* OMAP4470 OPP_NOM frequency
*/
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
@ -76,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
};
/* OMAP4460 OPP_NOM frequency */
/* OMAP4470 OPP_NOM (Low Power) frequency */
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
@ -198,6 +200,20 @@ struct dplls omap4460_dplls = {
.ddr = NULL
};
struct dplls omap4470_dplls = {
.mpu = mpu_dpll_params_1600mhz,
.core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
.step = 12660, /* 12.66 mV represented in uV */
@ -208,6 +224,7 @@ struct pmic_data twl6030_4430es1 = {
.pmic_write = omap_vc_bypass_send_value,
};
/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
.step = 12660, /* 12.66 mV represented in uV */
@ -271,6 +288,20 @@ struct vcores_data omap4460_volts = {
.mm.pmic = &twl6030,
};
struct vcores_data omap4470_volts = {
.mpu.value = 1200,
.mpu.addr = SMPS_REG_ADDR_SMPS1,
.mpu.pmic = &twl6030,
.core.value = 1126,
.core.addr = SMPS_REG_ADDR_SMPS1,
.core.pmic = &twl6030,
.mm.value = 1137,
.mm.addr = SMPS_REG_ADDR_SMPS1,
.mm.pmic = &twl6030,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@ -476,6 +507,11 @@ void hw_data_init(void)
*omap_vcores = &omap4460_volts;
break;
case OMAP4470_ES1_0:
*dplls_data = &omap4470_dplls;
*omap_vcores = &omap4470_volts;
break;
default:
printf("\n INVALID OMAP REVISION ");
}

7
arch/arm/include/asm/arch-omap4/clock.h
View File

@ -149,11 +149,16 @@
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
/* SMPS */
/* PMIC */
#define SMPS_I2C_SLAVE_ADDR 0x12
/* TWL6030 SMPS */
#define SMPS_REG_ADDR_VCORE1 0x55
#define SMPS_REG_ADDR_VCORE2 0x5B
#define SMPS_REG_ADDR_VCORE3 0x61
/* TWL6032 SMPS */
#define SMPS_REG_ADDR_SMPS1 0x55
#define SMPS_REG_ADDR_SMPS2 0x5B
#define SMPS_REG_ADDR_SMPS5 0x49
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000