ppc4xx: Add FPGA support and BSP commands for PMC440 boards
This patch adds some BSP commands and FPGA booting support for esd's PMC440 boards. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
72c5d52aed
commit
407843a582
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@ -0,0 +1,558 @@
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/*
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* (C) Copyright 2007
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* Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <asm/processor.h>
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#include "pmc440.h"
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int is_monarch(void);
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int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
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int eeprom_write_enable(unsigned dev_addr, int state);
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_BSP)
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static int got_fifoirq;
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static int got_hcirq;
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int fpga_interrupt(u32 arg)
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
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int rc = -1; /* not for us */
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u32 status = FPGA_IN32(&fpga->status);
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/* check for interrupt from fifo module */
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if (status & STATUS_FIFO_ISF) {
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/* disable this int source */
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FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
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rc = 0;
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got_fifoirq = 1; /* trigger backend */
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}
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if (status & STATUS_HOST_ISF) {
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FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
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rc = 0;
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got_hcirq = 1;
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}
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return rc;
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}
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int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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got_hcirq = 0;
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FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
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FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
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irq_install_handler(IRQ0_FPGA,
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(interrupt_handler_t *)fpga_interrupt,
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fpga);
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FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
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while (!got_hcirq) {
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/* Abort if ctrl-c was pressed */
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if (ctrlc()) {
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puts("\nAbort\n");
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break;
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}
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}
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if (got_hcirq)
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printf("Got interrupt!\n");
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FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
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irq_free_handler(IRQ0_FPGA);
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return 0;
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}
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U_BOOT_CMD(
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waithci, 1, 1, do_waithci,
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"waithci - Wait for host control interrupt\n",
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NULL
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);
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void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
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{
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u32 ctrl;
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while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
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printf("%5d %d %3d %08x",
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(*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
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FPGA_IN32(&fpga->fifo[f].data));
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if (ctrl & FIFO_OVERFLOW) {
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printf(" OVERFLOW\n");
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FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
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} else
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printf("\n");
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}
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}
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int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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int i;
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int n = 0;
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u32 ctrl, data, f;
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char str[] = "\\|/-";
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int abort = 0;
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int count = 0;
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int count2 = 0;
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switch (argc) {
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case 1:
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/* print all fifos status information */
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printf("fifo level status\n");
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printf("______________________________\n");
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for (i=0; i<FIFO_COUNT; i++) {
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ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
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printf(" %d %3d %s%s%s %s\n",
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i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
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ctrl & FIFO_FULL ? "FULL " : "",
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ctrl & FIFO_EMPTY ? "EMPTY " : "",
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ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
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ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
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}
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break;
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case 2:
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/* completely read out fifo 'n' */
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if (!strcmp(argv[1],"read")) {
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printf(" # fifo level data\n");
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printf("______________________________\n");
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for (i=0; i<FIFO_COUNT; i++)
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dump_fifo(fpga, i, &n);
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} else if (!strcmp(argv[1],"wait")) {
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got_fifoirq = 0;
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irq_install_handler(IRQ0_FPGA,
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(interrupt_handler_t *)fpga_interrupt,
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fpga);
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printf(" # fifo level data\n");
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printf("______________________________\n");
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/* enable all fifo interrupts */
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FPGA_OUT32(&fpga->hostctrl,
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HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
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for (i=0; i<FIFO_COUNT; i++) {
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/* enable interrupts from all fifos */
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FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
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}
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while (1) {
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/* wait loop */
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while (!got_fifoirq) {
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count++;
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if (!(count % 100)) {
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count2++;
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putc(0x08); /* backspace */
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putc(str[count2 % 4]);
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}
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/* Abort if ctrl-c was pressed */
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if ((abort = ctrlc())) {
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puts("\nAbort\n");
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break;
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}
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udelay(1000);
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}
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if (abort)
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break;
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/* simple fifo backend */
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if (got_fifoirq) {
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for (i=0; i<FIFO_COUNT; i++)
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dump_fifo(fpga, i, &n);
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got_fifoirq = 0;
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/* unmask global fifo irq */
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FPGA_OUT32(&fpga->hostctrl,
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HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
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}
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}
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/* disable all fifo interrupts */
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FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
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for (i=0; i<FIFO_COUNT; i++)
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FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
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irq_free_handler(IRQ0_FPGA);
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} else {
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printf("Usage:\nfifo %s\n", cmdtp->help);
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return 1;
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}
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break;
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case 4:
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case 5:
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if (!strcmp(argv[1],"write")) {
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/* get fifo number or fifo address */
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f = simple_strtoul(argv[2], NULL, 16);
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/* data paramter */
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data = simple_strtoul(argv[3], NULL, 16);
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/* get optional count parameter */
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n = 1;
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if (argc >= 5)
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n = (int)simple_strtoul(argv[4], NULL, 10);
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if (f < FIFO_COUNT) {
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printf("writing %d x %08x to fifo %d\n",
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n, data, f);
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for (i=0; i<n; i++)
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FPGA_OUT32(&fpga->fifo[f].data, data);
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} else {
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printf("writing %d x %08x to fifo port at address %08x\n",
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n, data, f);
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for (i=0; i<n; i++)
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out32(f, data);
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}
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} else {
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printf("Usage:\nfifo %s\n", cmdtp->help);
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return 1;
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}
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break;
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default:
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printf("Usage:\nfifo %s\n", cmdtp->help);
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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fifo, 5, 1, do_fifo,
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"fifo - Fifo module operations\n",
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"wait\nfifo read\n"
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"fifo write fifo(0..3) data [cnt=1]\n"
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"fifo write address(>=4) data [cnt=1]\n"
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" - without arguments: print all fifo's status\n"
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" - with 'wait' argument: interrupt driven read from all fifos\n"
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" - with 'read' argument: read current contents from all fifos\n"
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" - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n"
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);
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int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong sdsdp[5];
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ulong delay;
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int count=16;
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if (argc < 2) {
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printf("Usage:\nsbe %s\n", cmdtp->help);
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return -1;
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}
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if (argc > 1) {
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if (!strcmp(argv[1], "400")) {
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/* PLB=133MHz, PLB/PCI=4 */
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printf("Bootstrapping for 400MHz\n");
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sdsdp[0]=0x8678624e;
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sdsdp[1]=0x0947a030;
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sdsdp[2]=0x40082350;
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sdsdp[3]=0x0d050000;
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} else if (!strcmp(argv[1], "533")) {
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/* PLB=133MHz, PLB/PCI=3 */
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printf("Bootstrapping for 533MHz\n");
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sdsdp[0]=0x87788252;
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sdsdp[1]=0x095fa030;
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sdsdp[2]=0x40082350;
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sdsdp[3]=0x0d050000;
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} else if (!strcmp(argv[1], "667")) {
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/* PLB=133MHz, PLB/PCI=4 */
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printf("Bootstrapping for 667MHz\n");
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sdsdp[0]=0x8778a256;
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sdsdp[1]=0x0947a030;
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sdsdp[2]=0x40082350;
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sdsdp[3]=0x0d050000;
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} else if (!strcmp(argv[1], "test")) {
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/* TODO: this will replace the 667 MHz config above.
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* But it needs some more testing on a real 667 MHz CPU.
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*/
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printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n");
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sdsdp[0]=0x8778a256;
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sdsdp[1]=0x095fa030;
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sdsdp[2]=0x40082350;
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sdsdp[3]=0x0d050000;
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} else {
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printf("Usage:\nsbe %s\n", cmdtp->help);
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return -1;
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}
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}
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if (argc > 2) {
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sdsdp[4] = 0;
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if (argv[2][0]=='1')
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sdsdp[4]=0x19750100;
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else if (argv[2][0]=='0')
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sdsdp[4]=0x19750000;
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if (sdsdp[4])
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count += 4;
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}
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if (argc > 3) {
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delay = simple_strtoul(argv[3], NULL, 10);
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if (delay > 20)
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delay = 20;
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sdsdp[4] |= delay;
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}
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printf("Writing boot EEPROM ...\n");
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if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
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0, (uchar*)sdsdp, count) != 0)
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printf("bootstrap_eeprom_write failed\n");
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else
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printf("done (dump via 'i2c md 52 0.1 14')\n");
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return 0;
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}
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U_BOOT_CMD(
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sbe, 4, 0, do_setup_bootstrap_eeprom,
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"sbe - setup bootstrap eeprom\n",
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"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
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);
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#if defined(CONFIG_PRAM)
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#include <environment.h>
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extern env_t *env_ptr;
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int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u32 memsize;
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u32 pram, env_base;
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char *v;
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u32 param;
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ulong *lptr;
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memsize = gd->bd->bi_memsize;
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v = getenv("pram");
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if (v)
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pram = simple_strtoul(v, NULL, 10);
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else {
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printf("Error: pram undefined. Please define pram in KiB\n");
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return 1;
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}
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param = memsize - (pram << 10);
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printf("PARAM: @%08x\n", param);
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memset((void*)param, 0, (pram << 10));
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env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
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memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);
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lptr = (ulong*)memsize;
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*(--lptr) = CFG_ENV_SIZE;
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*(--lptr) = memsize - env_base;
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*(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
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*(--lptr) = 0;
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/* make sure data can be accessed through PCI */
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flush_dcache_range(param, param + (pram << 10) - 1);
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return 0;
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}
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U_BOOT_CMD(
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painit, 1, 1, do_painit,
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"painit - prepare PciAccess system\n",
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NULL
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);
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#endif /* CONFIG_PRAM */
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int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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if (argc > 1) {
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if (argv[1][0] == '0') {
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/* assert */
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printf("self-reset# asserted\n");
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out_be32((void*)GPIO0_TCR,
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in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
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} else {
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/* deassert */
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printf("self-reset# deasserted\n");
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out_be32((void*)GPIO0_TCR,
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in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
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}
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} else {
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printf("self-reset# is %s\n",
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in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
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"active" : "inactive");
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}
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return 0;
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}
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U_BOOT_CMD(
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selfreset, 2, 1, do_selfreset,
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"selfreset- assert self-reset# signal\n",
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NULL
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);
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int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
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/* requiers bootet FPGA and PLD_IOEN_N active */
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if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
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printf("Error: resetout requires a bootet FPGA\n");
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return -1;
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}
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if (argc > 1) {
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if (argv[1][0] == '0') {
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/* assert */
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printf("PMC-RESETOUT# asserted\n");
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FPGA_OUT32(&fpga->hostctrl,
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HOSTCTRL_PMCRSTOUT_GATE);
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} else {
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/* deassert */
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printf("PMC-RESETOUT# deasserted\n");
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FPGA_OUT32(&fpga->hostctrl,
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HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG);
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}
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} else {
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printf("PMC-RESETOUT# is %s\n",
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FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
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"inactive" : "active");
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}
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return 0;
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}
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U_BOOT_CMD(
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resetout, 2, 1, do_resetout,
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"resetout - assert PMC-RESETOUT# signal\n",
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NULL
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);
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int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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if (is_monarch()) {
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printf("This command is only supported in non-monarch mode\n");
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return -1;
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}
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if (argc > 1) {
|
||||
if (argv[1][0] == '0') {
|
||||
/* assert */
|
||||
printf("inta# asserted\n");
|
||||
out_be32((void*)GPIO1_TCR,
|
||||
in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
|
||||
} else {
|
||||
/* deassert */
|
||||
printf("inta# deasserted\n");
|
||||
out_be32((void*)GPIO1_TCR,
|
||||
in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
|
||||
}
|
||||
} else {
|
||||
printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
inta, 2, 1, do_inta,
|
||||
"inta - Assert/Deassert or query INTA# state in non-monarch mode\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
|
||||
/* test-only */
|
||||
int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong pciaddr;
|
||||
|
||||
if (argc > 1) {
|
||||
pciaddr = simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
pciaddr &= 0xf0000000;
|
||||
|
||||
/* map PCI address at 0xc0000000 in PLB space */
|
||||
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */
|
||||
out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */
|
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */
|
||||
out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */
|
||||
} else {
|
||||
printf("Usage:\npmm %s\n", cmdtp->help);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
pmm, 2, 1, do_pmm,
|
||||
"pmm - Setup pmm[1] registers\n",
|
||||
"<pciaddr> (pciaddr will be aligned to 256MB)\n"
|
||||
);
|
||||
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
|
||||
if (state < 0) {
|
||||
puts("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf("Write access for device 0x%0x is %sabled.\n",
|
||||
CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if ('0' == argv[1][0]) {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
|
||||
}
|
||||
if (state < 0) {
|
||||
puts("Setup of write access state failed.\n");
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||
"eepwren - Enable / disable / query EEPROM write access\n",
|
||||
NULL);
|
||||
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||
|
||||
#endif /* CONFIG_CMD_BSP */
|
||||
|
|
@ -0,0 +1,461 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <spartan2.h>
|
||||
#include <spartan3.h>
|
||||
#include <command.h>
|
||||
#include "fpga.h"
|
||||
#include "pmc440.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_FPGA)
|
||||
|
||||
#define USE_SP_CODE
|
||||
|
||||
#ifdef USE_SP_CODE
|
||||
Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
|
||||
fpga_pre_config_fn,
|
||||
fpga_pgm_fn,
|
||||
fpga_init_fn,
|
||||
NULL, /* err */
|
||||
fpga_done_fn,
|
||||
fpga_clk_fn,
|
||||
fpga_cs_fn,
|
||||
fpga_wr_fn,
|
||||
NULL, /* rdata */
|
||||
fpga_wdata_fn,
|
||||
fpga_busy_fn,
|
||||
fpga_abort_fn,
|
||||
fpga_post_config_fn,
|
||||
};
|
||||
#else
|
||||
Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
|
||||
fpga_pre_config_fn,
|
||||
fpga_pgm_fn,
|
||||
fpga_clk_fn,
|
||||
fpga_init_fn,
|
||||
fpga_done_fn,
|
||||
fpga_wr_fn,
|
||||
fpga_post_config_fn,
|
||||
};
|
||||
#endif
|
||||
|
||||
Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
|
||||
ngcc_fpga_pre_config_fn,
|
||||
ngcc_fpga_pgm_fn,
|
||||
ngcc_fpga_clk_fn,
|
||||
ngcc_fpga_init_fn,
|
||||
ngcc_fpga_done_fn,
|
||||
ngcc_fpga_wr_fn,
|
||||
ngcc_fpga_post_config_fn
|
||||
};
|
||||
|
||||
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
|
||||
XILINX_XC3S1200E_DESC(
|
||||
#ifdef USE_SP_CODE
|
||||
slave_parallel,
|
||||
#else
|
||||
slave_serial,
|
||||
#endif
|
||||
(void *)&pmc440_fpga_fns,
|
||||
0),
|
||||
XILINX_XC2S200_DESC(
|
||||
slave_serial,
|
||||
(void *)&ngcc_fpga_fns,
|
||||
0)
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Set the active-low FPGA reset signal.
|
||||
*/
|
||||
void fpga_reset(int assert)
|
||||
{
|
||||
debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
|
||||
if (assert) {
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
|
||||
debug("asserted\n");
|
||||
} else {
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
|
||||
debug("deasserted\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize the SelectMap interface. We assume that the mode and the
|
||||
* initial state of all of the port pins have already been set!
|
||||
*/
|
||||
void fpga_serialslave_init(void)
|
||||
{
|
||||
debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
|
||||
__LINE__);
|
||||
fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the FPGA's active-low SelectMap program line to the specified level
|
||||
*/
|
||||
int fpga_pgm_fn(int assert, int flush, int cookie)
|
||||
{
|
||||
debug("%s:%d: FPGA PROGRAM ",
|
||||
__FUNCTION__, __LINE__);
|
||||
|
||||
if (assert) {
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
|
||||
debug("asserted\n");
|
||||
} else {
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
|
||||
debug("deasserted\n");
|
||||
}
|
||||
return assert;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
|
||||
* asserted (low).
|
||||
*/
|
||||
int fpga_init_fn(int cookie)
|
||||
{
|
||||
if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef USE_SP_CODE
|
||||
int fpga_abort_fn(int cookie)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int fpga_cs_fn(int assert_cs, int flush, int cookie)
|
||||
{
|
||||
return assert_cs;
|
||||
}
|
||||
|
||||
|
||||
int fpga_busy_fn(int cookie)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Test the state of the active-high FPGA DONE pin
|
||||
*/
|
||||
int fpga_done_fn(int cookie)
|
||||
{
|
||||
if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* FPGA pre-configuration function. Just make sure that
|
||||
* FPGA reset is asserted to keep the FPGA from starting up after
|
||||
* configuration.
|
||||
*/
|
||||
int fpga_pre_config_fn(int cookie)
|
||||
{
|
||||
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
|
||||
fpga_reset(TRUE);
|
||||
|
||||
/* release init# */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
|
||||
/* disable PLD IOs */
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* FPGA post configuration function. Blip the FPGA reset line and then see if
|
||||
* the FPGA appears to be running.
|
||||
*/
|
||||
int fpga_post_config_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
int rc=0;
|
||||
char *s;
|
||||
|
||||
debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
|
||||
|
||||
/* enable PLD0..7 pins */
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
|
||||
|
||||
fpga_reset(TRUE);
|
||||
udelay (100);
|
||||
fpga_reset(FALSE);
|
||||
udelay (100);
|
||||
|
||||
FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
|
||||
|
||||
/* NGCC only: enable ledlink */
|
||||
if ((s = getenv("bd_type")) && !strcmp(s, "ngcc"))
|
||||
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int fpga_clk_fn(int assert_clk, int flush, int cookie)
|
||||
{
|
||||
if (assert_clk)
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
|
||||
else
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
|
||||
|
||||
return assert_clk;
|
||||
}
|
||||
|
||||
|
||||
int fpga_wr_fn(int assert_write, int flush, int cookie)
|
||||
{
|
||||
if (assert_write)
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
|
||||
else
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
|
||||
|
||||
return assert_write;
|
||||
}
|
||||
|
||||
#ifdef USE_SP_CODE
|
||||
int fpga_wdata_fn(uchar data, int flush, int cookie)
|
||||
{
|
||||
uchar val = data;
|
||||
ulong or = in_be32((void*)GPIO1_OR);
|
||||
int i = 7;
|
||||
do {
|
||||
/* Write data */
|
||||
if (val & 0x80)
|
||||
or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
|
||||
else
|
||||
or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
|
||||
|
||||
out_be32((void*)GPIO1_OR, or);
|
||||
|
||||
/* Assert the clock */
|
||||
or |= GPIO1_FPGA_CLK;
|
||||
out_be32((void*)GPIO1_OR, or);
|
||||
val <<= 1;
|
||||
i --;
|
||||
} while (i > 0);
|
||||
|
||||
/* Write last data bit (the 8th clock comes from the sp_load() code */
|
||||
if (val & 0x80)
|
||||
or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
|
||||
else
|
||||
or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
|
||||
|
||||
out_be32((void*)GPIO1_OR, or);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define NGCC_FPGA_PRG CLOCK_EN
|
||||
#define NGCC_FPGA_DATA RESET_OUT
|
||||
#define NGCC_FPGA_DONE CLOCK_IN
|
||||
#define NGCC_FPGA_INIT IRIGB_R_IN
|
||||
#define NGCC_FPGA_CLK CLOCK_OUT
|
||||
|
||||
void ngcc_fpga_serialslave_init(void)
|
||||
{
|
||||
debug("%s:%d: Initialize serial slave interface\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
|
||||
/* make sure program pin is inactive */
|
||||
ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the active-low FPGA reset signal.
|
||||
*/
|
||||
void ngcc_fpga_reset(int assert)
|
||||
{
|
||||
debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
|
||||
|
||||
if (assert) {
|
||||
FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
|
||||
debug("asserted\n");
|
||||
} else {
|
||||
FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
|
||||
debug("deasserted\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the FPGA's active-low SelectMap program line to the specified level
|
||||
*/
|
||||
int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
|
||||
|
||||
if (assert) {
|
||||
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
|
||||
debug("asserted\n");
|
||||
} else {
|
||||
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
|
||||
debug("deasserted\n");
|
||||
}
|
||||
|
||||
return assert;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
|
||||
* asserted (low).
|
||||
*/
|
||||
int ngcc_fpga_init_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
|
||||
if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
|
||||
debug("high\n");
|
||||
return 0;
|
||||
} else {
|
||||
debug("low\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test the state of the active-high FPGA DONE pin
|
||||
*/
|
||||
int ngcc_fpga_done_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
|
||||
if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
|
||||
debug("DONE high\n");
|
||||
return 1;
|
||||
} else {
|
||||
debug("low\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* FPGA pre-configuration function.
|
||||
*/
|
||||
int ngcc_fpga_pre_config_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
|
||||
|
||||
ngcc_fpga_reset(TRUE);
|
||||
FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
|
||||
|
||||
ngcc_fpga_reset(TRUE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* FPGA post configuration function. Blip the FPGA reset line and then see if
|
||||
* the FPGA appears to be running.
|
||||
*/
|
||||
int ngcc_fpga_post_config_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
|
||||
|
||||
udelay (100);
|
||||
ngcc_fpga_reset(FALSE);
|
||||
|
||||
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
if (assert_clk)
|
||||
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
|
||||
else
|
||||
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
|
||||
|
||||
return assert_clk;
|
||||
}
|
||||
|
||||
|
||||
int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
if (assert_write)
|
||||
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
|
||||
else
|
||||
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
|
||||
|
||||
return assert_write;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize the fpga. Return 1 on success, 0 on failure.
|
||||
*/
|
||||
int pmc440_init_fpga(void)
|
||||
{
|
||||
char *s;
|
||||
|
||||
debug("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
|
||||
__FUNCTION__, __LINE__, gd->reloc_off);
|
||||
fpga_init(gd->reloc_off);
|
||||
|
||||
fpga_serialslave_init ();
|
||||
debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
|
||||
fpga_add (fpga_xilinx, &fpga[0]);
|
||||
|
||||
/* NGCC only */
|
||||
if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
|
||||
ngcc_fpga_serialslave_init ();
|
||||
debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
|
||||
fpga_add (fpga_xilinx, &fpga[1]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_FPGA */
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
extern int pmc440_init_fpga(void);
|
||||
|
||||
extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
|
||||
extern int fpga_init_fn(int cookie);
|
||||
extern int fpga_err_fn(int cookie);
|
||||
extern int fpga_done_fn(int cookie);
|
||||
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
|
||||
extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
|
||||
extern int fpga_wr_fn(int assert_write, int flush, int cookie);
|
||||
extern int fpga_wdata_fn (uchar data, int flush, int cookie);
|
||||
extern int fpga_read_data_fn(unsigned char *data, int cookie);
|
||||
extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
|
||||
extern int fpga_busy_fn(int cookie);
|
||||
extern int fpga_abort_fn(int cookie );
|
||||
extern int fpga_pre_config_fn(int cookie );
|
||||
extern int fpga_post_config_fn(int cookie );
|
||||
|
||||
extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
|
||||
extern int ngcc_fpga_init_fn(int cookie);
|
||||
extern int ngcc_fpga_done_fn(int cookie);
|
||||
extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
|
||||
extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
|
||||
extern int ngcc_fpga_pre_config_fn(int cookie );
|
||||
extern int ngcc_fpga_post_config_fn(int cookie );
|
||||
Loading…
Reference in New Issue