rockchip: rk3036: Add clock driver
Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
huang lin
Simon Glass
parent
fc0fada094
commit
3f2ef13924
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@ -0,0 +1,168 @@
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK3036_H
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#define _ASM_ARCH_CRU_RK3036_H
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#include <common.h>
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_HZ (600 * 1000000)
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#define GPLL_HZ (594 * 1000000)
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#define CORE_PERI_HZ 150000000
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#define CORE_ACLK_HZ 300000000
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#define CPU_ACLK_HZ 150000000
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#define CPU_HCLK_HZ 300000000
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#define CPU_PCLK_HZ 300000000
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#define PERI_ACLK_HZ 148500000
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#define PERI_HCLK_HZ 148500000
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#define PERI_PCLK_HZ 74250000
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struct rk3036_cru {
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struct rk3036_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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} pll[4];
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unsigned int cru_mode_con;
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unsigned int cru_clksel_con[35];
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unsigned int cru_clkgate_con[11];
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unsigned int reserved;
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unsigned int cru_glb_srst_fst_value;
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unsigned int cru_glb_srst_snd_value;
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unsigned int reserved1[2];
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unsigned int cru_softrst_con[9];
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unsigned int cru_misc_con;
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unsigned int reserved2[2];
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unsigned int cru_glb_cnt_th;
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unsigned int cru_sdmmc_con[2];
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unsigned int cru_sdio_con[2];
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unsigned int cru_emmc_con[2];
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unsigned int reserved3;
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unsigned int cru_rst_st;
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unsigned int reserved4[0x23];
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unsigned int cru_pll_mask_con;
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};
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check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
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struct pll_div {
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u32 refdiv;
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u32 fbdiv;
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u32 postdiv1;
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u32 postdiv2;
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u32 frac;
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};
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enum {
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/* PLLCON0*/
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PLL_POSTDIV1_MASK = 7,
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PLL_POSTDIV1_SHIFT = 12,
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PLL_FBDIV_MASK = 0xfff,
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PLL_FBDIV_SHIFT = 0,
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/* PLLCON1 */
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PLL_DSMPD_MASK = 1,
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PLL_DSMPD_SHIFT = 12,
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PLL_LOCK_STATUS_MASK = 1,
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PLL_LOCK_STATUS_SHIFT = 10,
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PLL_POSTDIV2_MASK = 7,
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PLL_POSTDIV2_SHIFT = 6,
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PLL_REFDIV_MASK = 0x3f,
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PLL_REFDIV_SHIFT = 0,
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PLL_RST_SHIFT = 14,
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/* CRU_MODE */
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GPLL_MODE_MASK = 3,
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GPLL_MODE_SHIFT = 12,
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GPLL_MODE_SLOW = 0,
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GPLL_MODE_NORM,
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GPLL_MODE_DEEP,
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DPLL_MODE_MASK = 1,
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DPLL_MODE_SHIFT = 4,
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DPLL_MODE_SLOW = 0,
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DPLL_MODE_NORM,
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APLL_MODE_MASK = 1,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_SLOW = 0,
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APLL_MODE_NORM,
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/* CRU_CLK_SEL0_CON */
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CPU_CLK_PLL_SEL_MASK = 3,
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CPU_CLK_PLL_SEL_SHIFT = 14,
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CPU_CLK_PLL_SEL_APLL = 0,
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CPU_CLK_PLL_SEL_DPLL,
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CPU_CLK_PLL_SEL_GPLL,
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ACLK_CPU_DIV_MASK = 0x1f,
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ACLK_CPU_DIV_SHIFT = 8,
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CORE_CLK_PLL_SEL_MASK = 1,
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CORE_CLK_PLL_SEL_SHIFT = 7,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL,
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CORE_DIV_CON_MASK = 0x1f,
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CORE_DIV_CON_SHIFT = 0,
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/* CRU_CLK_SEL1_CON */
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CPU_PCLK_DIV_MASK = 7,
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CPU_PCLK_DIV_SHIFT = 12,
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CPU_HCLK_DIV_MASK = 3,
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CPU_HCLK_DIV_SHIFT = 8,
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CORE_ACLK_DIV_MASK = 7,
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CORE_ACLK_DIV_SHIFT = 4,
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CORE_PERI_DIV_MASK = 0xf,
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CORE_PERI_DIV_SHIFT = 0,
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/* CRU_CLKSEL10_CON */
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PERI_PLL_SEL_MASK = 3,
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PERI_PLL_SEL_SHIFT = 14,
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PERI_PLL_APLL = 0,
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PERI_PLL_DPLL,
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PERI_PLL_GPLL,
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PERI_PCLK_DIV_MASK = 3,
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PERI_PCLK_DIV_SHIFT = 12,
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PERI_HCLK_DIV_MASK = 3,
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PERI_HCLK_DIV_SHIFT = 8,
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PERI_ACLK_DIV_MASK = 0x1f,
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PERI_ACLK_DIV_SHIFT = 0,
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/* CRU_CLKSEL11_CON */
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SDIO_DIV_MASK = 0x7f,
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SDIO_DIV_SHIFT = 8,
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MMC0_DIV_MASK = 0x7f,
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MMC0_DIV_SHIFT = 0,
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/* CRU_CLKSEL12_CON */
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EMMC_PLL_MASK = 3,
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EMMC_PLL_SHIFT = 12,
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EMMC_SEL_APLL = 0,
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EMMC_SEL_DPLL,
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EMMC_SEL_GPLL,
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EMMC_SEL_24M,
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SDIO_PLL_MASK = 3,
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SDIO_PLL_SHIFT = 10,
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SDIO_SEL_APLL = 0,
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SDIO_SEL_DPLL,
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SDIO_SEL_GPLL,
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SDIO_SEL_24M,
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MMC0_PLL_MASK = 3,
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MMC0_PLL_SHIFT = 8,
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MMC0_SEL_APLL = 0,
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MMC0_SEL_DPLL,
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MMC0_SEL_GPLL,
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MMC0_SEL_24M,
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EMMC_DIV_MASK = 0x7f,
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EMMC_DIV_SHIFT = 0,
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/* CRU_SOFTRST5_CON */
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DDRCTRL_PSRST_SHIFT = 11,
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DDRCTRL_SRST_SHIFT = 10,
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DDRPHY_PSRST_SHIFT = 9,
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DDRPHY_SRST_SHIFT = 8,
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};
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#endif
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@ -6,5 +6,6 @@
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#
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obj-$(CONFIG_CLK) += clk-uclass.o
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obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
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obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox.o
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@ -0,0 +1,414 @@
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/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3036.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/periph.h>
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#include <dm/lists.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rk3036_clk_plat {
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enum rk_clk_id clk_id;
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};
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struct rk3036_clk_priv {
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struct rk3036_cru *cru;
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ulong rate;
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};
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enum {
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VCO_MAX_HZ = 2400U * 1000000,
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VCO_MIN_HZ = 600 * 1000000,
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OUTPUT_MAX_HZ = 2400U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#define RATE_TO_DIV(input_rate, output_rate) \
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((input_rate) / (output_rate) - 1);
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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/* use interge mode*/
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static inline unsigned int log2(unsigned int value)
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{
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return fls(value) - 1;
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}
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static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rk_pll_id(clk_id);
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struct rk3036_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
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vco=%u Hz, output=%u Hz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/* use interger mode */
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rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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rk_clrsetreg(&pll->con0,
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PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
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(div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
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rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
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PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
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(div->postdiv2 << PLL_POSTDIV2_SHIFT |
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div->refdiv << PLL_REFDIV_SHIFT));
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/* waiting for pll lock */
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while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
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udelay(1);
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return 0;
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}
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static void rkclk_init(struct rk3036_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK << GPLL_MODE_SHIFT |
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APLL_MODE_MASK << APLL_MODE_SHIFT,
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
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APLL_MODE_SLOW << APLL_MODE_SHIFT);
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/* init pll */
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rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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/*
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* select apll as core clock pll source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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* core hz : apll = 1:1
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*/
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aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
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assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
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pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
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assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT |
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CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT,
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CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
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0 << CORE_DIV_CON_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT |
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CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
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aclk_div << CORE_ACLK_DIV_SHIFT |
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pclk_div << CORE_PERI_DIV_SHIFT);
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/*
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* select apll as cpu clock pll source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = APLL_HZ / CPU_ACLK_HZ - 1;
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assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f);
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pclk_div = APLL_HZ / CPU_PCLK_HZ - 1;
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assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7);
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hclk_div = APLL_HZ / CPU_HCLK_HZ - 1;
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assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT |
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ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT,
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CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT |
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aclk_div << ACLK_CPU_DIV_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
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CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
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pclk_div << CPU_PCLK_DIV_SHIFT |
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hclk_div << CPU_HCLK_DIV_SHIFT);
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/*
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* select gpll as peri clock pll source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ ==
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PERI_ACLK_HZ && (pclk_div < 0x4));
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pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ ==
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PERI_ACLK_HZ && pclk_div < 0x8);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT |
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PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
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PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
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PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
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PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
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pclk_div << PERI_PCLK_DIV_SHIFT |
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hclk_div << PERI_HCLK_DIV_SHIFT |
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aclk_div << PERI_ACLK_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK << GPLL_MODE_SHIFT |
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APLL_MODE_MASK << APLL_MODE_SHIFT,
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GPLL_MODE_NORM << GPLL_MODE_SHIFT |
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APLL_MODE_NORM << APLL_MODE_SHIFT);
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}
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/* Get pll rate by id */
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static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
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enum rk_clk_id clk_id)
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{
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uint32_t refdiv, fbdiv, postdiv1, postdiv2;
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uint32_t con;
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int pll_id = rk_pll_id(clk_id);
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struct rk3036_pll *pll = &cru->pll[pll_id];
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static u8 clk_shift[CLK_COUNT] = {
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0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
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GPLL_MODE_SHIFT, 0xff
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};
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static u8 clk_mask[CLK_COUNT] = {
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0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
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GPLL_MODE_MASK, 0xff
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};
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uint shift;
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uint mask;
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con = readl(&cru->cru_mode_con);
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shift = clk_shift[clk_id];
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mask = clk_mask[clk_id];
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switch ((con >> shift) & mask) {
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case GPLL_MODE_SLOW:
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return OSC_HZ;
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case GPLL_MODE_NORM:
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/* normal mode */
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con = readl(&pll->con0);
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postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK;
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fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK;
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con = readl(&pll->con1);
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postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK;
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refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK;
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return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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case GPLL_MODE_DEEP:
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default:
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return 32768;
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}
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}
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static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
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enum periph_id periph)
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{
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uint src_rate;
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uint div, mux;
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u32 con;
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||||
|
||||
switch (periph) {
|
||||
case PERIPH_ID_EMMC:
|
||||
con = readl(&cru->cru_clksel_con[12]);
|
||||
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
|
||||
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
|
||||
break;
|
||||
case PERIPH_ID_SDCARD:
|
||||
con = readl(&cru->cru_clksel_con[12]);
|
||||
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
|
||||
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
|
||||
return DIV_TO_RATE(src_rate, div);
|
||||
}
|
||||
|
||||
static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
|
||||
enum periph_id periph, uint freq)
|
||||
{
|
||||
int src_clk_div;
|
||||
int mux;
|
||||
|
||||
debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
|
||||
|
||||
/* mmc clock auto divide 2 in internal */
|
||||
src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
|
||||
|
||||
if (src_clk_div > 0x7f) {
|
||||
src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
|
||||
mux = EMMC_SEL_24M;
|
||||
} else {
|
||||
mux = EMMC_SEL_GPLL;
|
||||
}
|
||||
|
||||
switch (periph) {
|
||||
case PERIPH_ID_EMMC:
|
||||
rk_clrsetreg(&cru->cru_clksel_con[12],
|
||||
EMMC_PLL_MASK << EMMC_PLL_SHIFT |
|
||||
EMMC_DIV_MASK << EMMC_DIV_SHIFT,
|
||||
mux << EMMC_PLL_SHIFT |
|
||||
(src_clk_div - 1) << EMMC_DIV_SHIFT);
|
||||
break;
|
||||
case PERIPH_ID_SDCARD:
|
||||
rk_clrsetreg(&cru->cru_clksel_con[11],
|
||||
MMC0_PLL_MASK << MMC0_PLL_SHIFT |
|
||||
MMC0_DIV_MASK << MMC0_DIV_SHIFT,
|
||||
mux << MMC0_PLL_SHIFT |
|
||||
(src_clk_div - 1) << MMC0_DIV_SHIFT);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
|
||||
}
|
||||
|
||||
static ulong rk3036_clk_get_rate(struct udevice *dev)
|
||||
{
|
||||
struct rk3036_clk_plat *plat = dev_get_platdata(dev);
|
||||
struct rk3036_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
debug("%s\n", dev->name);
|
||||
return rkclk_pll_get_rate(priv->cru, plat->clk_id);
|
||||
}
|
||||
|
||||
static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate)
|
||||
{
|
||||
debug("%s\n", dev->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
|
||||
{
|
||||
struct rk3036_clk_priv *priv = dev_get_priv(dev);
|
||||
ulong new_rate;
|
||||
|
||||
switch (periph) {
|
||||
case PERIPH_ID_EMMC:
|
||||
new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),
|
||||
periph, rate);
|
||||
break;
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
return new_rate;
|
||||
}
|
||||
|
||||
static struct clk_ops rk3036_clk_ops = {
|
||||
.get_rate = rk3036_clk_get_rate,
|
||||
.set_rate = rk3036_clk_set_rate,
|
||||
.set_periph_rate = rk3036_set_periph_rate,
|
||||
};
|
||||
|
||||
static int rk3036_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct rk3036_clk_plat *plat = dev_get_platdata(dev);
|
||||
struct rk3036_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (plat->clk_id != CLK_OSC) {
|
||||
struct rk3036_clk_priv *parent_priv = dev_get_priv(dev->parent);
|
||||
|
||||
priv->cru = parent_priv->cru;
|
||||
return 0;
|
||||
}
|
||||
priv->cru = (struct rk3036_cru *)dev_get_addr(dev);
|
||||
rkclk_init(priv->cru);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *const clk_name[] = {
|
||||
"osc",
|
||||
"apll",
|
||||
"dpll",
|
||||
"cpll",
|
||||
"gpll",
|
||||
"mpll",
|
||||
};
|
||||
|
||||
static int rk3036_clk_bind(struct udevice *dev)
|
||||
{
|
||||
struct rk3036_clk_plat *plat = dev_get_platdata(dev);
|
||||
int pll, ret;
|
||||
|
||||
/* We only need to set up the root clock */
|
||||
if (dev->of_offset == -1) {
|
||||
plat->clk_id = CLK_OSC;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Create devices for P main clocks */
|
||||
for (pll = 1; pll < CLK_COUNT; pll++) {
|
||||
struct udevice *child;
|
||||
struct rk3036_clk_plat *cplat;
|
||||
|
||||
debug("%s %s\n", __func__, clk_name[pll]);
|
||||
ret = device_bind_driver(dev, "clk_rk3036", clk_name[pll],
|
||||
&child);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cplat = dev_get_platdata(child);
|
||||
cplat->clk_id = pll;
|
||||
}
|
||||
|
||||
/* The reset driver does not have a device node, so bind it here */
|
||||
ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev);
|
||||
if (ret)
|
||||
debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id rk3036_clk_ids[] = {
|
||||
{ .compatible = "rockchip,rk3036-cru" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_rk3036) = {
|
||||
.name = "clk_rk3036",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = rk3036_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
|
||||
.platdata_auto_alloc_size = sizeof(struct rk3036_clk_plat),
|
||||
.ops = &rk3036_clk_ops,
|
||||
.bind = rk3036_clk_bind,
|
||||
.probe = rk3036_clk_probe,
|
||||
};
|
||||
Loading…
Reference in New Issue