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ARM: exynos: clock: modify the set_mmc_clk for exynos4 

Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Jaehoon Chung 2014-05-16 13:59:50 +09:00 committed by Minkyu Kang
parent 58209dface
commit 39c4975622
2 changed files with 16 additions and 5 deletions
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16
arch/arm/cpu/armv7/exynos/clock.c
View File

@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{ {
struct exynos4_clock *clk = struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock(); (struct exynos4_clock *)samsung_get_base_clock();
unsigned int addr; unsigned int addr, clear_bit, set_bit;
/* /*
* CLK_DIV_FSYS1 * CLK_DIV_FSYS1
@ -877,20 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
* CLK_DIV_FSYS2 * CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
* CLK_DIV_FSYS3 * CLK_DIV_FSYS3
* MMC4_PRE_RATIO [15:8] * MMC4_RATIO [3:0]
*/ */
if (dev_index < 2) { if (dev_index < 2) {
addr = (unsigned int)&clk->div_fsys1; addr = (unsigned int)&clk->div_fsys1;
} else if (dev_index == 4) { clear_bit = MASK_PRE_RATIO(dev_index);
set_bit = SET_PRE_RATIO(dev_index, div);
} else if (dev_index == 4) {
addr = (unsigned int)&clk->div_fsys3; addr = (unsigned int)&clk->div_fsys3;
dev_index -= 4; dev_index -= 4;
/* MMC4 is controlled with the MMC4_RATIO value */
clear_bit = MASK_RATIO(dev_index);
set_bit = SET_RATIO(dev_index, div);
} else { } else {
addr = (unsigned int)&clk->div_fsys2; addr = (unsigned int)&clk->div_fsys2;
dev_index -= 2; dev_index -= 2;
clear_bit = MASK_PRE_RATIO(dev_index);
set_bit = SET_PRE_RATIO(dev_index, div);
} }
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), clrsetbits_le32(addr, clear_bit, set_bit);
(div & 0xff) << ((dev_index << 4) + 8));
} }
/* exynos5: set the mmc clock */ /* exynos5: set the mmc clock */

5
arch/arm/include/asm/arch-exynos/clk.h
View File

@ -16,6 +16,11 @@
#define BPLL 5 #define BPLL 5
#define RPLL 6 #define RPLL 6
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8))
#define SET_RATIO(x, y) ((y & 0xf) << (x << 4))
enum pll_src_bit { enum pll_src_bit {
EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL, EXYNOS_SRC_EPLL,