arm: Remove mx31_litekit board
This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Tom Rini
parent
bc0840bcb7
commit
36d14178fc
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@ -260,10 +260,6 @@ config TARGET_TT01
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bool "Support tt01"
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select CPU_ARM1136
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config TARGET_IMX31_LITEKIT
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bool "Support imx31_litekit"
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select CPU_ARM1136
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config TARGET_WOODBURN
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bool "Support woodburn"
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select CPU_ARM1136
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@ -823,7 +819,6 @@ source "board/imx31_phycore/Kconfig"
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source "board/isee/igep0033/Kconfig"
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source "board/jornada/Kconfig"
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source "board/karo/tx25/Kconfig"
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source "board/logicpd/imx31_litekit/Kconfig"
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source "board/maxbcm/Kconfig"
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source "board/mpl/vcma9/Kconfig"
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source "board/olimex/mx23_olinuxino/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_IMX31_LITEKIT
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config SYS_BOARD
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default "imx31_litekit"
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config SYS_VENDOR
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default "logicpd"
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config SYS_SOC
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default "mx31"
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config SYS_CONFIG_NAME
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default "imx31_litekit"
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endif
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@ -1,6 +0,0 @@
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IMX31_LITEKIT BOARD
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#M: -
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S: Maintained
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F: board/logicpd/imx31_litekit/
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F: include/configs/imx31_litekit.h
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F: configs/imx31_litekit_defconfig
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := imx31_litekit.o
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obj-y += lowlevel_init.o
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@ -1,91 +0,0 @@
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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int board_early_init_f(void)
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{
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/* CS0: Nor Flash */
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static const struct mxc_weimcs cs0 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
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};
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/* CS4: Network Controller */
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static const struct mxc_weimcs cs4 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
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};
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mxc_setup_weimcs(0, &cs0);
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mxc_setup_weimcs(4, &cs4);
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
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/* SPI2 */
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mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
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mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
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mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
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mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
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mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
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mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
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mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
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/* start SPI2 clock */
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: i.MX31 Litekit\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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@ -1,87 +0,0 @@
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/imx-regs.h>
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.macro REG reg, val
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ldr r2, =\reg
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ldr r3, =\val
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str r3, [r2]
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.endm
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.macro REG8 reg, val
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ldr r2, =\reg
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ldr r3, =\val
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strb r3, [r2]
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.endm
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.macro DELAY loops
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ldr r2, =\loops
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1:
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subs r2, r2, #1
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nop
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bcs 1b
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.endm
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.globl lowlevel_init
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lowlevel_init:
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REG IPU_CONF, IPU_CONF_DI_EN
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REG CCM_CCMR, 0x074B0BF5
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DELAY 0x40000
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
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REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
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REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
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REG 0x43FAC26C, 0 /* SDCLK */
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REG 0x43FAC270, 0 /* CAS */
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REG 0x43FAC274, 0 /* RAS */
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REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
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REG 0x43FAC284, 0 /* DQM3 */
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REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
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REG 0x43FAC28C, 0
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REG 0x43FAC290, 0
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REG 0x43FAC294, 0
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REG 0x43FAC298, 0
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REG 0x43FAC29C, 0
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REG 0x43FAC2A0, 0
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REG 0x43FAC2A4, 0
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REG 0x43FAC2A8, 0
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REG 0x43FAC2AC, 0
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REG 0x43FAC2B0, 0
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REG 0x43FAC2B4, 0
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REG 0x43FAC2B8, 0
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REG 0x43FAC2BC, 0
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REG 0x43FAC2C0, 0
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REG 0x43FAC2C4, 0
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REG 0x43FAC2C8, 0
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REG 0x43FAC2CC, 0
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REG 0x43FAC2D0, 0
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REG 0x43FAC2D4, 0
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REG 0x43FAC2D8, 0
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REG 0x43FAC2DC, 0
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REG 0xB8001010, 0x00000004
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REG 0xB8001004, 0x006ac73a
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REG 0xB8001000, 0x92100000
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REG 0x80000f00, 0x12344321
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REG 0xB8001000, 0xa2100000
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REG 0x80000000, 0x12344321
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REG 0x80000000, 0x12344321
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REG 0xB8001000, 0xb2100000
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REG8 0x80000033, 0xda
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REG8 0x81000000, 0xff
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REG 0xB8001000, 0x82226080
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REG 0x80000000, 0xDEADBEEF
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REG 0xB8001010, 0x0000000c
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mov pc, lr
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@ -1,4 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_IMX31_LITEKIT=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_SYS_PROMPT="uboot> "
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@ -1,171 +0,0 @@
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/*
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* (C) Copyright 2004
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Kshitij Gupta <kshitij@ti.com>
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*
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* Configuration settings for the LogicPD i.MX31 Litekit board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_MX31 1 /* This is a mx31 */
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#define CONFIG_MX31_CLK32 32000
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_TEXT_BASE 0xa0000000
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#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE
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/* Temporarily disabled */
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#if 0
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_FIT 1
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#define CONFIG_FIT_VERBOSE 1
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#endif
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_MXC_GPIO
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#define CONFIG_HARD_SPI 1
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#define CONFIG_MXC_SPI 1
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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/* PMIC Controller */
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#define CONFIG_POWER
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#define CONFIG_POWER_SPI
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#define CONFIG_POWER_FSL
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_BITLEN 32
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#define CONFIG_RTC_MC13XXX
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/***********************************************************
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* Command definition
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***********************************************************/
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_NAND
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.23.168
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#define CONFIG_SERVERIP 192.168.23.2
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
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"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
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#define CONFIG_SMC911X 1
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#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
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#define CONFIG_SMC911X_32_BIT 1
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x10000
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#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
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#define CONFIG_CMDLINE_EDITING 1
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE
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#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_BASE CS0_BASE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_SIZE (64 * 1024)
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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/*
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* JFFS2 partitions
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*/
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#undef CONFIG_CMD_MTDPARTS
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#define CONFIG_JFFS2_DEV "nor0"
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/*
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* NAND flash
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*/
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#define CONFIG_NAND_MXC
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#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
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#define CONFIG_MXC_NAND_HWECC
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#endif /* __CONFIG_H */
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