MIPS: add board qemu-mips64 support
Both big-endian and little-endian are tested with below commands: Rom version: (Default, Now we config it as rom version) qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic Ram version: qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Zhi-zhou Zhang
Daniel Schwierzeck
parent
ff9b0cb8b4
commit
32afad783e
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@ -0,0 +1,45 @@
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).o
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START = start.o
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COBJS-y = cpu.o interrupts.o time.o cache.o
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SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
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START := $(addprefix $(obj),$(START))
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all: $(obj).depend $(START) $(LIB)
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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@ -0,0 +1,229 @@
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/*
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* Cache-handling routined for MIPS CPUs
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#define RA t9
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/*
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* 16kB is the maximum size of instruction and data caches on MIPS 4K,
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* 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
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*
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* Note that the above size is the maximum size of primary cache. U-Boot
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* doesn't have L2 cache support for now.
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*/
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#define MIPS_MAX_CACHE_SIZE 0x10000
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#define INDEX_BASE CKSEG0
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.macro cache_op op addr
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.set push
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.set noreorder
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.set mips3
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cache \op, 0(\addr)
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.set pop
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.endm
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.macro f_fill64 dst, offset, val
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
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#if LONGSIZE == 4
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LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
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#endif
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.endm
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/*
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* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
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*/
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LEAF(mips_init_icache)
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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/* clear tag to invalidate */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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1: cache_op INDEX_STORE_TAG_I t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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/* fill once, so data field parity is correct */
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PTR_LI t0, INDEX_BASE
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2: cache_op FILL t0
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PTR_ADDU t0, a2
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bne t0, t1, 2b
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/* invalidate again - prudent but not strictly neccessary */
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PTR_LI t0, INDEX_BASE
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1: cache_op INDEX_STORE_TAG_I t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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END(mips_init_icache)
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/*
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* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
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*/
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LEAF(mips_init_dcache)
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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1: cache_op INDEX_STORE_TAG_D t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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/* load from each line (in cached space) */
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PTR_LI t0, INDEX_BASE
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2: LONG_L zero, 0(t0)
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PTR_ADDU t0, a2
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bne t0, t1, 2b
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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1: cache_op INDEX_STORE_TAG_D t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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END(mips_init_dcache)
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/*
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* mips_cache_reset - low level initialisation of the primary caches
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*
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* This routine initialises the primary caches to ensure that they have good
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* parity. It must be called by the ROM before any cached locations are used
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* to prevent the possibility of data with bad parity being written to memory.
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*
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* To initialise the instruction cache it is essential that a source of data
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* with good parity is available. This routine will initialise an area of
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* memory starting at location zero to be used as a source of parity.
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*
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* RETURNS: N/A
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*
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*/
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NESTED(mips_cache_reset, 0, ra)
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move RA, ra
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li t2, CONFIG_SYS_ICACHE_SIZE
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li t3, CONFIG_SYS_DCACHE_SIZE
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li t8, CONFIG_SYS_CACHELINE_SIZE
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li v0, MIPS_MAX_CACHE_SIZE
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/*
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* Now clear that much memory starting from zero.
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*/
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PTR_LI a0, CKSEG1
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PTR_ADDU a1, a0, v0
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2: PTR_ADDIU a0, 64
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f_fill64 a0, -64, zero
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bne a0, a1, 2b
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/*
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* The caches are probably in an indeterminate state,
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* so we force good parity into them by doing an
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* invalidate, load/fill, invalidate for each line.
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*/
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/*
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* Assume bottom of RAM will generate good parity for the cache.
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*/
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/*
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* Initialize the I-cache first,
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*/
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move a1, t2
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move a2, t8
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PTR_LA v1, mips_init_icache
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jalr v1
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/*
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* then initialize D-cache.
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*/
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move a1, t3
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move a2, t8
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PTR_LA v1, mips_init_dcache
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jalr v1
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jr RA
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END(mips_cache_reset)
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/*
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* dcache_status - get cache status
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*
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* RETURNS: 0 - cache disabled; 1 - cache enabled
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*
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*/
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LEAF(dcache_status)
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mfc0 t0, CP0_CONFIG
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li t1, CONF_CM_UNCACHED
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andi t0, t0, CONF_CM_CMASK
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move v0, zero
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beq t0, t1, 2f
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li v0, 1
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2: jr ra
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END(dcache_status)
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/*
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* dcache_disable - disable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_disable)
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mfc0 t0, CP0_CONFIG
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li t1, -8
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and t0, t0, t1
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ori t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_disable)
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/*
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* dcache_enable - enable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_enable)
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mfc0 t0, CP0_CONFIG
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ori t0, CONF_CM_CMASK
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xori t0, CONF_CM_CMASK
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ori t0, CONF_CM_CACHABLE_NONCOHERENT
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_enable)
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@ -0,0 +1,40 @@
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# Default optimization level for MIPS64
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#
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# Note: Toolchains with binutils prior to v2.16
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# are no longer supported by U-Boot MIPS tree!
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#
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MIPSFLAGS = -march=mips64
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PLATFORM_CPPFLAGS += $(MIPSFLAGS)
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PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
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ifdef CONFIG_SYS_BIG_ENDIAN
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PLATFORM_LDFLAGS += -m elf64btsmip
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else
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PLATFORM_LDFLAGS += -m elf64ltsmip
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endif
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CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
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@ -0,0 +1,111 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
|
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* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
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* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheops.h>
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#include <asm/reboot.h>
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#define cache_op(op, addr) \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noreorder\n" \
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" .set mips64\n" \
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" cache %0, %1\n" \
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" .set pop\n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void __attribute__((weak)) _machine_restart(void)
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{
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fprintf(stderr, "*** reset failed ***\n");
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while (1)
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/* NOP */;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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_machine_restart();
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return 0;
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
|
||||||
|
|
||||||
|
/* aend will be miscalculated when size is zero, so we return here */
|
||||||
|
if (size == 0)
|
||||||
|
return;
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
cache_op(HIT_WRITEBACK_INV_D, addr);
|
||||||
|
cache_op(HIT_INVALIDATE_I, addr);
|
||||||
|
if (addr == aend)
|
||||||
|
break;
|
||||||
|
addr += lsize;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void flush_dcache_range(ulong start_addr, ulong stop)
|
||||||
|
{
|
||||||
|
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||||
|
unsigned long addr = start_addr & ~(lsize - 1);
|
||||||
|
unsigned long aend = (stop - 1) & ~(lsize - 1);
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
cache_op(HIT_WRITEBACK_INV_D, addr);
|
||||||
|
if (addr == aend)
|
||||||
|
break;
|
||||||
|
addr += lsize;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void invalidate_dcache_range(ulong start_addr, ulong stop)
|
||||||
|
{
|
||||||
|
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||||
|
unsigned long addr = start_addr & ~(lsize - 1);
|
||||||
|
unsigned long aend = (stop - 1) & ~(lsize - 1);
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
cache_op(HIT_INVALIDATE_D, addr);
|
||||||
|
if (addr == aend)
|
||||||
|
break;
|
||||||
|
addr += lsize;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
|
||||||
|
{
|
||||||
|
write_c0_entrylo0(low0);
|
||||||
|
write_c0_pagemask(pagemask);
|
||||||
|
write_c0_entrylo1(low1);
|
||||||
|
write_c0_entryhi(hi);
|
||||||
|
write_c0_index(index);
|
||||||
|
tlb_write_indexed();
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/mipsregs.h>
|
||||||
|
|
||||||
|
void enable_interrupts(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
int disable_interrupts(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,256 @@
|
||||||
|
/*
|
||||||
|
* Startup Code for MIPS64 CPU-core
|
||||||
|
*
|
||||||
|
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any dlater version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm-offsets.h>
|
||||||
|
#include <config.h>
|
||||||
|
#include <asm/regdef.h>
|
||||||
|
#include <asm/mipsregs.h>
|
||||||
|
|
||||||
|
#ifndef CONFIG_SYS_MIPS_CACHE_MODE
|
||||||
|
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For the moment disable interrupts, mark the kernel mode and
|
||||||
|
* set ST0_KX so that the CPU does not spit fire when using
|
||||||
|
* 64-bit addresses.
|
||||||
|
*/
|
||||||
|
.macro setup_c0_status set clr
|
||||||
|
.set push
|
||||||
|
mfc0 t0, CP0_STATUS
|
||||||
|
or t0, ST0_CU0 | \set | 0x1f | \clr
|
||||||
|
xor t0, 0x1f | \clr
|
||||||
|
mtc0 t0, CP0_STATUS
|
||||||
|
.set noreorder
|
||||||
|
sll zero, 3 # ehb
|
||||||
|
.set pop
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.set noreorder
|
||||||
|
|
||||||
|
.globl _start
|
||||||
|
.text
|
||||||
|
_start:
|
||||||
|
.org 0x000
|
||||||
|
b reset
|
||||||
|
nop
|
||||||
|
.org 0x080
|
||||||
|
b romReserved
|
||||||
|
nop
|
||||||
|
.org 0x100
|
||||||
|
b romReserved
|
||||||
|
nop
|
||||||
|
.org 0x180
|
||||||
|
b romReserved
|
||||||
|
nop
|
||||||
|
.org 0x200
|
||||||
|
b romReserved
|
||||||
|
nop
|
||||||
|
.org 0x280
|
||||||
|
b romReserved
|
||||||
|
nop
|
||||||
|
.org 0x300
|
||||||
|
b romReserved
|
||||||
|
nop
|
||||||
|
.org 0x380
|
||||||
|
b romReserved
|
||||||
|
nop
|
||||||
|
.org 0x480
|
||||||
|
b romReserved
|
||||||
|
nop
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We hope there are no more reserved vectors!
|
||||||
|
* 128 * 8 == 1024 == 0x400
|
||||||
|
* so this is address R_VEC+0x400 == 0xbfc00400
|
||||||
|
*/
|
||||||
|
.org 0x500
|
||||||
|
.align 4
|
||||||
|
reset:
|
||||||
|
|
||||||
|
/* Clear watch registers */
|
||||||
|
dmtc0 zero, CP0_WATCHLO
|
||||||
|
dmtc0 zero, CP0_WATCHHI
|
||||||
|
|
||||||
|
/* WP(Watch Pending), SW0/1 should be cleared */
|
||||||
|
mtc0 zero, CP0_CAUSE
|
||||||
|
|
||||||
|
setup_c0_status ST0_KX 0
|
||||||
|
|
||||||
|
/* Init Timer */
|
||||||
|
mtc0 zero, CP0_COUNT
|
||||||
|
mtc0 zero, CP0_COMPARE
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
/* CONFIG0 register */
|
||||||
|
dli t0, CONF_CM_UNCACHED
|
||||||
|
mtc0 t0, CP0_CONFIG
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Initialize $gp */
|
||||||
|
bal 1f
|
||||||
|
nop
|
||||||
|
.dword _gp
|
||||||
|
1:
|
||||||
|
ld gp, 0(ra)
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
/* Initialize any external memory */
|
||||||
|
dla t9, lowlevel_init
|
||||||
|
jalr t9
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* Initialize caches... */
|
||||||
|
dla t9, mips_cache_reset
|
||||||
|
jalr t9
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* ... and enable them */
|
||||||
|
dli t0, CONFIG_SYS_MIPS_CACHE_MODE
|
||||||
|
mtc0 t0, CP0_CONFIG
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set up temporary stack */
|
||||||
|
dli t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
|
||||||
|
dla sp, 0(t0)
|
||||||
|
|
||||||
|
dla t9, board_init_f
|
||||||
|
jr t9
|
||||||
|
nop
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
* a0 = addr_sp
|
||||||
|
* a1 = gd
|
||||||
|
* a2 = destination address
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
.ent relocate_code
|
||||||
|
relocate_code:
|
||||||
|
move sp, a0 # set new stack pointer
|
||||||
|
|
||||||
|
dli t0, CONFIG_SYS_MONITOR_BASE
|
||||||
|
dla t3, in_ram
|
||||||
|
ld t2, -24(t3) # t2 <-- uboot_end_data
|
||||||
|
move t1, a2
|
||||||
|
move s2, a2 # s2 <-- destination address
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Fix $gp:
|
||||||
|
*
|
||||||
|
* New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
|
||||||
|
*/
|
||||||
|
move t8, gp
|
||||||
|
dsub gp, CONFIG_SYS_MONITOR_BASE
|
||||||
|
dadd gp, a2 # gp now adjusted
|
||||||
|
dsub s1, gp, t8 # s1 <-- relocation offset
|
||||||
|
|
||||||
|
/*
|
||||||
|
* t0 = source address
|
||||||
|
* t1 = target address
|
||||||
|
* t2 = source end address
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save destination address and size for dlater usage in flush_cache()
|
||||||
|
*/
|
||||||
|
move s0, a1 # save gd in s0
|
||||||
|
move a0, t1 # a0 <-- destination addr
|
||||||
|
dsub a1, t2, t0 # a1 <-- size
|
||||||
|
|
||||||
|
1:
|
||||||
|
lw t3, 0(t0)
|
||||||
|
sw t3, 0(t1)
|
||||||
|
daddu t0, 4
|
||||||
|
ble t0, t2, 1b
|
||||||
|
daddu t1, 4
|
||||||
|
|
||||||
|
/* If caches were enabled, we would have to flush them here. */
|
||||||
|
|
||||||
|
/* a0 & a1 are already set up for flush_cache(start, size) */
|
||||||
|
dla t9, flush_cache
|
||||||
|
jalr t9
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* Jump to where we've relocated ourselves */
|
||||||
|
daddi t0, s2, in_ram - _start
|
||||||
|
jr t0
|
||||||
|
nop
|
||||||
|
|
||||||
|
.dword _gp
|
||||||
|
.dword _GLOBAL_OFFSET_TABLE_
|
||||||
|
.dword uboot_end_data
|
||||||
|
.dword uboot_end
|
||||||
|
.dword num_got_entries
|
||||||
|
|
||||||
|
in_ram:
|
||||||
|
/*
|
||||||
|
* Now we want to update GOT.
|
||||||
|
*
|
||||||
|
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
|
||||||
|
* generated by GNU ld. Skip these reserved entries from relocation.
|
||||||
|
*/
|
||||||
|
ld t3, -8(t0) # t3 <-- num_got_entries
|
||||||
|
ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
|
||||||
|
ld t9, -40(t0) # t9 <-- _gp
|
||||||
|
dsub t8, t9 # compute offset
|
||||||
|
dadd t8, t8, gp # t8 now holds relocated _G_O_T_
|
||||||
|
daddi t8, t8, 16 # skipping first two entries
|
||||||
|
dli t2, 2
|
||||||
|
1:
|
||||||
|
ld t1, 0(t8)
|
||||||
|
beqz t1, 2f
|
||||||
|
dadd t1, s1
|
||||||
|
sd t1, 0(t8)
|
||||||
|
2:
|
||||||
|
daddi t2, 1
|
||||||
|
blt t2, t3, 1b
|
||||||
|
daddi t8, 8
|
||||||
|
|
||||||
|
/* Clear BSS */
|
||||||
|
ld t1, -24(t0) # t1 <-- uboot_end_data
|
||||||
|
ld t2, -16(t0) # t2 <-- uboot_end
|
||||||
|
dadd t1, s1 # adjust pointers
|
||||||
|
dadd t2, s1
|
||||||
|
|
||||||
|
dsub t1, 8
|
||||||
|
1:
|
||||||
|
daddi t1, 8
|
||||||
|
bltl t1, t2, 1b
|
||||||
|
sd zero, 0(t1)
|
||||||
|
|
||||||
|
move a0, s0 # a0 <-- gd
|
||||||
|
dla t9, board_init_r
|
||||||
|
jr t9
|
||||||
|
move a1, s2
|
||||||
|
|
||||||
|
.end relocate_code
|
||||||
|
|
||||||
|
/* Exception handlers */
|
||||||
|
romReserved:
|
||||||
|
b romReserved
|
||||||
|
|
@ -0,0 +1,87 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/mipsregs.h>
|
||||||
|
|
||||||
|
static unsigned long timestamp;
|
||||||
|
|
||||||
|
/* how many counter cycles in a jiffy */
|
||||||
|
#define CYCLES_PER_JIFFY \
|
||||||
|
(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
|
||||||
|
|
||||||
|
/*
|
||||||
|
* timer without interrupts
|
||||||
|
*/
|
||||||
|
|
||||||
|
int timer_init(void)
|
||||||
|
{
|
||||||
|
/* Set up the timer for the first expiration. */
|
||||||
|
timestamp = 0;
|
||||||
|
write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
ulong get_timer(ulong base)
|
||||||
|
{
|
||||||
|
unsigned int count;
|
||||||
|
unsigned int expirelo = read_c0_compare();
|
||||||
|
|
||||||
|
/* Check to see if we have missed any timestamps. */
|
||||||
|
count = read_c0_count();
|
||||||
|
while ((count - expirelo) < 0x7fffffff) {
|
||||||
|
expirelo += CYCLES_PER_JIFFY;
|
||||||
|
timestamp++;
|
||||||
|
}
|
||||||
|
write_c0_compare(expirelo);
|
||||||
|
|
||||||
|
return timestamp - base;
|
||||||
|
}
|
||||||
|
|
||||||
|
void __udelay(unsigned long usec)
|
||||||
|
{
|
||||||
|
unsigned int tmo;
|
||||||
|
|
||||||
|
tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
|
||||||
|
while ((tmo - read_c0_count()) < 0x7fffffff)
|
||||||
|
/*NOP*/;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function is derived from PowerPC code (read timebase as long long).
|
||||||
|
* On MIPS it just returns the timer value.
|
||||||
|
*/
|
||||||
|
unsigned long long get_ticks(void)
|
||||||
|
{
|
||||||
|
return get_timer(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function is derived from PowerPC code (timebase clock frequency).
|
||||||
|
* On MIPS it returns the number of timer ticks per second.
|
||||||
|
*/
|
||||||
|
ulong get_tbclk(void)
|
||||||
|
{
|
||||||
|
return CONFIG_SYS_HZ;
|
||||||
|
}
|
||||||
|
|
@ -24,7 +24,11 @@
|
||||||
/*
|
/*
|
||||||
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
||||||
*/
|
*/
|
||||||
|
#if defined(CONFIG_64BIT)
|
||||||
|
OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
|
||||||
|
#else
|
||||||
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
|
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
|
||||||
|
#endif
|
||||||
OUTPUT_ARCH(mips)
|
OUTPUT_ARCH(mips)
|
||||||
ENTRY(_start)
|
ENTRY(_start)
|
||||||
SECTIONS
|
SECTIONS
|
||||||
|
|
@ -63,7 +67,11 @@ SECTIONS
|
||||||
}
|
}
|
||||||
|
|
||||||
uboot_end_data = .;
|
uboot_end_data = .;
|
||||||
|
#if defined(CONFIG_64BIT)
|
||||||
|
num_got_entries = (__got_end - __got_start) >> 3;
|
||||||
|
#else
|
||||||
num_got_entries = (__got_end - __got_start) >> 2;
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
#endif
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.sbss : { *(.sbss*) }
|
.sbss : { *(.sbss*) }
|
||||||
|
|
|
||||||
|
|
@ -404,6 +404,8 @@ M5485HFE m68k mcf547x_8x m548xevb freescale -
|
||||||
microblaze-generic microblaze microblaze microblaze-generic xilinx
|
microblaze-generic microblaze microblaze microblaze-generic xilinx
|
||||||
qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN
|
qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN
|
||||||
qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
|
qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
|
||||||
|
qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN
|
||||||
|
qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN
|
||||||
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
|
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
|
||||||
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
|
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
|
||||||
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
|
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,59 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* Wolfgang Denk Engineering, <wd@denx.de>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
||||||
|
*/
|
||||||
|
OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
|
||||||
|
OUTPUT_ARCH(mips)
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
*(.text*)
|
||||||
|
}
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.data : { *(.data*) }
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
_gp = ALIGN(16) + 0x7ff0;
|
||||||
|
|
||||||
|
.got : {
|
||||||
|
__got_start = .;
|
||||||
|
*(.got)
|
||||||
|
__got_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
|
.sdata : { *(.sdata*) }
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
__bss_start = .;
|
||||||
|
.sbss (NOLOAD) : { *(.sbss*) }
|
||||||
|
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
|
||||||
|
|
||||||
|
_end = .;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,175 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This file contains the configuration parameters for qemu-mips64 target.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
#define CONFIG_MIPS64 /* MIPS64 CPU core */
|
||||||
|
#define CONFIG_QEMU_MIPS
|
||||||
|
#define CONFIG_MISC_INIT_R
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
|
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
|
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||||
|
#undef CONFIG_BOOTARGS
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"addmisc=setenv bootargs ${bootargs} " \
|
||||||
|
"console=ttyS0,${baudrate} " \
|
||||||
|
"panic=1\0" \
|
||||||
|
"bootfile=/tftpboot/vmlinux\0" \
|
||||||
|
"load=tftp ffffffff80500000 ${u-boot}\0" \
|
||||||
|
""
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND "bootp;bootelf"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOTP options
|
||||||
|
*/
|
||||||
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||||
|
#define CONFIG_BOOTP_BOOTPATH
|
||||||
|
#define CONFIG_BOOTP_GATEWAY
|
||||||
|
#define CONFIG_BOOTP_HOSTNAME
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration.
|
||||||
|
*/
|
||||||
|
#include <config_cmd_default.h>
|
||||||
|
|
||||||
|
#define CONFIG_CMD_ELF
|
||||||
|
#define CONFIG_CMD_FAT
|
||||||
|
#define CONFIG_CMD_EXT2
|
||||||
|
#undef CONFIG_CMD_LOADB
|
||||||
|
#undef CONFIG_CMD_LOADS
|
||||||
|
#define CONFIG_CMD_DHCP
|
||||||
|
|
||||||
|
#define CONFIG_DRIVER_NE2000
|
||||||
|
#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550
|
||||||
|
#define CONFIG_SYS_NS16550_SERIAL
|
||||||
|
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||||
|
#define CONFIG_SYS_NS16550_CLK 115200
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8
|
||||||
|
#define CONFIG_CONS_INDEX 1
|
||||||
|
|
||||||
|
#define CONFIG_CMD_IDE
|
||||||
|
#define CONFIG_DOS_PARTITION
|
||||||
|
|
||||||
|
#define CONFIG_SYS_IDE_MAXBUS 2
|
||||||
|
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
|
||||||
|
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
|
||||||
|
#define CONFIG_SYS_ATA_DATA_OFFSET 0
|
||||||
|
#define CONFIG_SYS_ATA_REG_OFFSET 0
|
||||||
|
#define CONFIG_SYS_ATA_BASE_ADDR 0xffffffffb4000000
|
||||||
|
|
||||||
|
#define CONFIG_SYS_IDE_MAXDEVICE 4
|
||||||
|
|
||||||
|
#define CONFIG_CMD_RARP
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||||
|
|
||||||
|
/* Monitor Command Prompt */
|
||||||
|
#if defined(CONFIG_SYS_LITTLE_ENDIAN)
|
||||||
|
#define CONFIG_SYS_PROMPT "qemu-mips64el # "
|
||||||
|
#else
|
||||||
|
#define CONFIG_SYS_PROMPT "qemu-mips64 # "
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_AUTO_COMPLETE
|
||||||
|
#define CONFIG_CMDLINE_EDITING
|
||||||
|
#define CONFIG_SYS_HUSH_PARSER
|
||||||
|
|
||||||
|
/* Console I/O Buffer Size */
|
||||||
|
#define CONFIG_SYS_CBSIZE 256
|
||||||
|
/* Print Buffer Size */
|
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||||
|
/* max number of command args */
|
||||||
|
#define CONFIG_SYS_MAXARGS 16
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN 128*1024
|
||||||
|
|
||||||
|
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MHZ 132
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_HZ 1000
|
||||||
|
|
||||||
|
/* Cached addr */
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
|
||||||
|
|
||||||
|
/* default load address */
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
|
||||||
|
#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* FLASH and environment organization
|
||||||
|
*/
|
||||||
|
/* The following #defines are needed to get flash environment right */
|
||||||
|
#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* Rom version */
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
|
||||||
|
|
||||||
|
/* We boot from this flash, selected with dip switch */
|
||||||
|
#define CONFIG_SYS_FLASH_BASE 0xffffffffbfc00000
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 128
|
||||||
|
#define CONFIG_SYS_FLASH_CFI
|
||||||
|
#define CONFIG_FLASH_CFI_DRIVER
|
||||||
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||||
|
|
||||||
|
#define CONFIG_ENV_IS_IN_FLASH
|
||||||
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||||
|
|
||||||
|
/* Address and size of Primary Environment Sector */
|
||||||
|
#define CONFIG_ENV_SIZE 0x8000
|
||||||
|
|
||||||
|
#define CONFIG_ENV_OVERWRITE 1
|
||||||
|
|
||||||
|
#define MEM_SIZE 128
|
||||||
|
|
||||||
|
#define CONFIG_LZMA
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Cache Configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_DCACHE_SIZE 16384
|
||||||
|
#define CONFIG_SYS_ICACHE_SIZE 16384
|
||||||
|
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */
|
||||||
Loading…
Reference in New Issue