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sunxi: fix SMP bit for V3s SoC 

The cache of Cortex-A7 is only enabled if the SMP bit is set, but the
SMP bit of V3s is wrongly left unset, because I thought that it's not
SMP-capable.

Fix this.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
This commit is contained in:
Icenowy Zheng 2017-08-12 17:24:24 +08:00
parent a297a99445
commit 32ab1804cd
1 changed files with 2 additions and 3 deletions
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5
arch/arm/mach-sunxi/board.c
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@ -184,11 +184,10 @@ void s_init(void)
/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
#endif
#if (defined CONFIG_MACH_SUN6I || \
#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN8I || \
defined CONFIG_MACH_SUN9I) && \
!defined CONFIG_MACH_SUN8I_V3S
defined CONFIG_MACH_SUN9I
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"