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x86: Convert to use driver model pci on quark/galileo 

Move to driver model pci for Intel quark/galileo.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2015-09-03 05:37:26 -07:00 committed by Simon Glass
parent 316fd3920f
commit 31b5aebd5e
6 changed files with 7 additions and 90 deletions
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1
arch/x86/cpu/quark/Makefile
View File

@ -6,4 +6,3 @@
obj-y += car.o dram.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
obj-$(CONFIG_PCI) += pci.o

70
arch/x86/cpu/quark/pci.c
View File

@ -1,70 +0,0 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
#include <asm/arch/device.h>
DECLARE_GLOBAL_DATA_PTR;
void board_pci_setup_hose(struct pci_controller *hose)
{
hose->first_busno = 0;
hose->last_busno = 0;
/* PCI memory space */
pci_set_region(hose->regions + 0,
CONFIG_PCI_MEM_BUS,
CONFIG_PCI_MEM_PHYS,
CONFIG_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_IO_BUS,
CONFIG_PCI_IO_PHYS,
CONFIG_PCI_IO_SIZE,
PCI_REGION_IO);
pci_set_region(hose->regions + 2,
CONFIG_PCI_PREF_BUS,
CONFIG_PCI_PREF_PHYS,
CONFIG_PCI_PREF_SIZE,
PCI_REGION_PREFETCH);
pci_set_region(hose->regions + 3,
0,
0,
gd->ram_size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
}
int board_pci_post_scan(struct pci_controller *hose)
{
return 0;
}
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
* TODO:
*
* For some unknown reason, the PCI enumeration process hangs
* when it scans to the PCIe root port 0 (D23:F0) & 1 (D23:F1).
*
* For now we just skip these two devices, and this needs to
* be revisited later.
*/
if (dev == QUARK_HOST_BRIDGE ||
dev == QUARK_PCIE0 || dev == QUARK_PCIE1) {
return 1;
}
return 0;
}

5
arch/x86/cpu/quark/quark.c
View File

@ -136,7 +136,6 @@ static void quark_enable_legacy_seg(void)
int arch_cpu_init(void)
{
struct pci_controller *hose;
int ret;
post_code(POST_CPU_INIT);
@ -148,10 +147,6 @@ int arch_cpu_init(void)
if (ret)
return ret;
ret = pci_early_init_hose(&hose);
if (ret)
return ret;
/*
* Quark SoC has some non-standard BARs (excluding PCI standard BARs)
* which need be initialized with suggested values

8
arch/x86/dts/galileo.dts
View File

@ -54,8 +54,11 @@
pci {
#address-cells = <3>;
#size-cells = <2>;
compatible = "intel,pci";
device_type = "pci";
compatible = "pci-x86";
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
pciuart0: uart@14,5 {
compatible = "pci8086,0936.00",
@ -63,6 +66,7 @@
"pciclass,070002",
"pciclass,0700",
"x86-uart";
u-boot,dm-pre-reloc;
reg = <0x0000a500 0x0 0x0 0x0 0x0
0x0200a510 0x0 0x0 0x0 0x0>;
reg-shift = <2>;

1
configs/galileo_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_VSNPRINTF=y

12
include/configs/galileo.h
View File

@ -20,18 +20,6 @@
/* ns16550 UART is memory-mapped in Quark SoC */
#undef CONFIG_SYS_NS16550_PORT_MAPPED
#define CONFIG_PCI_MEM_BUS 0x90000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x20000000
#define CONFIG_PCI_PREF_BUS 0xb0000000
#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
#define CONFIG_PCI_PREF_SIZE 0x20000000
#define CONFIG_PCI_IO_BUS 0x2000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xe000
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP