powerpc: Remove __ilog2_u64 and ffs4 from bitops
Remove __ilog2_u64 and ffs4 from powerpc bitops to align with the kernel implementation. Use the generic __ffs64 instead of a custom powerpc implementation. Cc: York Sun <yorksun@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
This commit is contained in:
parent
f8fdb81f6c
commit
2d2f490dd5
|
@ -9,6 +9,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <linux/log2.h>
|
||||
|
||||
int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
|
||||
{
|
||||
|
@ -20,7 +21,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
|
|||
if (start == 0)
|
||||
start_align = 1ull << (LAW_SIZE_2G + 1);
|
||||
else
|
||||
start_align = 1ull << (ffs64(start) - 1);
|
||||
start_align = 1ull << (__ffs64(start) - 1);
|
||||
law_sz = min(start_align, sz);
|
||||
law_sz_enc = __ilog2_u64(law_sz) - 1;
|
||||
|
||||
|
@ -40,7 +41,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
|
|||
if (sz) {
|
||||
start += law_sz;
|
||||
|
||||
start_align = 1ull << (ffs64(start) - 1);
|
||||
start_align = 1ull << (__ffs64(start) - 1);
|
||||
law_sz = min(start_align, sz);
|
||||
law_sz_enc = __ilog2_u64(law_sz) - 1;
|
||||
ecm = &immap->sysconf.ddrlaw[1];
|
||||
|
|
|
@ -14,6 +14,8 @@
|
|||
#include <addr_map.h>
|
||||
#endif
|
||||
|
||||
#include <linux/log2.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void invalidate_tlb(u8 tlb)
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
#include <linux/compiler.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/log2.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -187,7 +188,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
|
|||
if (start == 0)
|
||||
start_align = 1ull << (LAW_SIZE_32G + 1);
|
||||
else
|
||||
start_align = 1ull << (ffs64(start) - 1);
|
||||
start_align = 1ull << (__ffs64(start) - 1);
|
||||
law_sz = min(start_align, sz);
|
||||
law_sz_enc = __ilog2_u64(law_sz) - 1;
|
||||
|
||||
|
@ -202,7 +203,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
|
|||
if (sz) {
|
||||
start += law_sz;
|
||||
|
||||
start_align = 1ull << (ffs64(start) - 1);
|
||||
start_align = 1ull << (__ffs64(start) - 1);
|
||||
law_sz = min(start_align, sz);
|
||||
law_sz_enc = __ilog2_u64(law_sz) - 1;
|
||||
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
#define _PPC_BITOPS_H
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm-generic/bitops/__ffs.h>
|
||||
|
||||
extern void set_bit(int nr, volatile void *addr);
|
||||
extern void clear_bit(int nr, volatile void *addr);
|
||||
|
@ -209,16 +210,6 @@ static inline int fls64(__u64 x)
|
|||
#error BITS_PER_LONG not 32 or 64
|
||||
#endif
|
||||
|
||||
static inline int __ilog2_u64(u64 n)
|
||||
{
|
||||
return fls64(n) - 1;
|
||||
}
|
||||
|
||||
static inline int ffs64(u64 x)
|
||||
{
|
||||
return __ilog2_u64(x & -x) + 1ull;
|
||||
}
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/*
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#define _FSL_LAW_H_
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <linux/log2.h>
|
||||
|
||||
#define LAW_EN 0x80000000
|
||||
|
||||
|
|
|
@ -7,6 +7,8 @@
|
|||
#ifndef _FSL_SRIO_H_
|
||||
#define _FSL_SRIO_H_
|
||||
|
||||
#include <linux/log2.h>
|
||||
|
||||
enum atmu_size {
|
||||
ATMU_SIZE_4K = 0xb,
|
||||
ATMU_SIZE_8K,
|
||||
|
|
Loading…
Reference in New Issue