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imx: mx6: ddr correct tRFC and tXS 

To Chip density 4Gb, tRFC should be 300ns, see
"Table 61 — Refresh parameters by device density" of JESD79-3E.
tXS(min) is max(5nCK, tRFC(min) + 10ns).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan 2015-08-17 16:10:59 +08:00 committed by Stefano Babic
parent 24139754f5
commit 2cd8cd06bb
1 changed files with 2 additions and 2 deletions
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4
arch/arm/cpu/armv7/mx6/ddr.c
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@ -357,8 +357,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
txs = DIV_ROUND_UP(170000, clkper) - 1;
break;
case 4: /* 4Gb per chip */
trfc = DIV_ROUND_UP(260000, clkper) - 1;
txs = DIV_ROUND_UP(270000, clkper) - 1;
trfc = DIV_ROUND_UP(300000, clkper) - 1;
txs = DIV_ROUND_UP(310000, clkper) - 1;
break;
case 8: /* 8Gb per chip */
trfc = DIV_ROUND_UP(350000, clkper) - 1;