net: altera_tse: use data type u32 for regs and desc
Use data type u32/u16/u8 for regs and desc, as it is more portable. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Thomas Chou
parent
fba54a5d61
commit
2cd0a52ece
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@ -27,12 +27,12 @@ static inline void alt_sgdma_construct_descriptor(
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struct alt_sgdma_descriptor *next,
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void *read_addr,
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void *write_addr,
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unsigned short length_or_eop,
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u16 length_or_eop,
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int generate_eop,
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int read_fixed,
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int write_fixed_or_sop)
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{
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unsigned char val;
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u8 val;
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/*
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* Mark the "next" descriptor as "not" owned by hardware. This prevents
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@ -100,7 +100,7 @@ static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
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static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
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struct alt_sgdma_descriptor *desc)
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{
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unsigned int val;
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u32 val;
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/* Point the controller at the descriptor */
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writel(virt_to_phys(desc), ®s->next_descriptor_pointer);
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@ -121,7 +121,7 @@ static void tse_adjust_link(struct altera_tse_priv *priv,
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struct phy_device *phydev)
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{
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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unsigned int refvar;
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u32 refvar;
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if (!phydev->link) {
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debug("%s: No link.\n", phydev->dev->name);
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@ -230,7 +230,7 @@ static void altera_tse_stop(struct udevice *dev)
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struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
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struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
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struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
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unsigned int status;
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u32 status;
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int ret;
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ulong ctime;
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@ -266,7 +266,7 @@ static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct altera_tse_priv *priv = bus->priv;
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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unsigned int value;
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u32 value;
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/* set mdio address */
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writel(addr, &mac_dev->mdio_phy1_addr);
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@ -337,7 +337,7 @@ static int altera_tse_write_hwaddr(struct udevice *dev)
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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struct eth_pdata *pdata = dev_get_platdata(dev);
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u8 *hwaddr = pdata->enetaddr;
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unsigned int mac_lo, mac_hi;
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u32 mac_lo, mac_hi;
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mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
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(hwaddr[1] << 8) | hwaddr[0];
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@ -362,7 +362,7 @@ static int altera_tse_start(struct udevice *dev)
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{
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struct altera_tse_priv *priv = dev_get_priv(dev);
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struct alt_tse_mac *mac_dev = priv->mac_dev;
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unsigned int val;
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u32 val;
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int ret;
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/* need to create sgdma */
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@ -54,34 +54,34 @@
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*
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*/
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struct alt_sgdma_descriptor {
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unsigned int source; /* the address of data to be read. */
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unsigned int source_pad;
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u32 source; /* the address of data to be read. */
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u32 source_pad;
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unsigned int destination; /* the address to write data */
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unsigned int destination_pad;
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u32 destination; /* the address to write data */
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u32 destination_pad;
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unsigned int next; /* the next descriptor in the list. */
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unsigned int next_pad;
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u32 next; /* the next descriptor in the list. */
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u32 next_pad;
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unsigned short bytes_to_transfer; /* the number of bytes to transfer */
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unsigned char read_burst;
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unsigned char write_burst;
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u16 bytes_to_transfer; /* the number of bytes to transfer */
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u8 read_burst;
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u8 write_burst;
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unsigned short actual_bytes_transferred;/* bytes transferred by DMA */
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unsigned char descriptor_status;
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unsigned char descriptor_control;
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u16 actual_bytes_transferred;/* bytes transferred by DMA */
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u8 descriptor_status;
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u8 descriptor_control;
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} __packed_1_;
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/* SG-DMA Control/Status Slave registers map */
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struct alt_sgdma_registers {
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unsigned int status;
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unsigned int status_pad[3];
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unsigned int control;
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unsigned int control_pad[3];
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unsigned int next_descriptor_pointer;
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unsigned int descriptor_pad[3];
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u32 status;
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u32 status_pad[3];
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u32 control;
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u32 control_pad[3];
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u32 next_descriptor_pointer;
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u32 descriptor_pad[3];
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};
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/* TSE Stuff */
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@ -98,47 +98,47 @@ struct alt_sgdma_registers {
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/* MAC register Space */
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struct alt_tse_mac {
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unsigned int megacore_revision;
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unsigned int scratch_pad;
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unsigned int command_config;
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unsigned int mac_addr_0;
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unsigned int mac_addr_1;
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unsigned int max_frame_length;
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unsigned int pause_quanta;
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unsigned int rx_sel_empty_threshold;
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unsigned int rx_sel_full_threshold;
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unsigned int tx_sel_empty_threshold;
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unsigned int tx_sel_full_threshold;
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unsigned int rx_almost_empty_threshold;
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unsigned int rx_almost_full_threshold;
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unsigned int tx_almost_empty_threshold;
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unsigned int tx_almost_full_threshold;
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unsigned int mdio_phy0_addr;
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unsigned int mdio_phy1_addr;
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u32 megacore_revision;
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u32 scratch_pad;
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u32 command_config;
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u32 mac_addr_0;
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u32 mac_addr_1;
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u32 max_frame_length;
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u32 pause_quanta;
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u32 rx_sel_empty_threshold;
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u32 rx_sel_full_threshold;
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u32 tx_sel_empty_threshold;
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u32 tx_sel_full_threshold;
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u32 rx_almost_empty_threshold;
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u32 rx_almost_full_threshold;
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u32 tx_almost_empty_threshold;
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u32 tx_almost_full_threshold;
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u32 mdio_phy0_addr;
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u32 mdio_phy1_addr;
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unsigned int reserved1[0x29];
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u32 reserved1[0x29];
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/*FIFO control register. */
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unsigned int tx_cmd_stat;
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unsigned int rx_cmd_stat;
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u32 tx_cmd_stat;
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u32 rx_cmd_stat;
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unsigned int reserved2[0x44];
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u32 reserved2[0x44];
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/*Registers 0 to 31 within PHY device 0/1 */
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unsigned int mdio_phy0[0x20];
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unsigned int mdio_phy1[0x20];
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u32 mdio_phy0[0x20];
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u32 mdio_phy1[0x20];
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/*4 Supplemental MAC Addresses */
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unsigned int supp_mac_addr_0_0;
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unsigned int supp_mac_addr_0_1;
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unsigned int supp_mac_addr_1_0;
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unsigned int supp_mac_addr_1_1;
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unsigned int supp_mac_addr_2_0;
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unsigned int supp_mac_addr_2_1;
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unsigned int supp_mac_addr_3_0;
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unsigned int supp_mac_addr_3_1;
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u32 supp_mac_addr_0_0;
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u32 supp_mac_addr_0_1;
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u32 supp_mac_addr_1_0;
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u32 supp_mac_addr_1_1;
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u32 supp_mac_addr_2_0;
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u32 supp_mac_addr_2_1;
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u32 supp_mac_addr_3_0;
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u32 supp_mac_addr_3_1;
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unsigned int reserved3[0x38];
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u32 reserved3[0x38];
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};
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struct altera_tse_priv {
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