spi: davinci: add support for multiple bus and chip select
Currently davinci spi driver supports only bus 0 cs 0. This patch allows driver to support bus 1 and bus 2 with configurable number of chip selects. Also defaults are selected in a way to avoid regression on other platforms that uses davinci spi driver and has only one spi bus. Signed-off-by: Rex Chang <rchang@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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@ -32,7 +32,27 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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if (!ds)
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if (!ds)
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return NULL;
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return NULL;
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ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE;
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ds->slave.bus = bus;
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ds->slave.cs = cs;
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switch (bus) {
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case SPI0_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
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break;
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#endif
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default: /* Invalid bus number */
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return NULL;
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}
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ds->freq = max_hz;
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ds->freq = max_hz;
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return &ds->slave;
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return &ds->slave;
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@ -59,7 +79,7 @@ int spi_claim_bus(struct spi_slave *slave)
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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/* CS, CLK, SIMO and SOMI are functional pins */
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/* CS, CLK, SIMO and SOMI are functional pins */
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writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK |
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writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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/* setup format */
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/* setup format */
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@ -264,7 +284,30 @@ out:
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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{
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return bus == 0 && cs == 0;
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int ret = 0;
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switch (bus) {
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case SPI0_BUS:
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if (cs < SPI0_NUM_CS)
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ret = 1;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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if (cs < SPI1_NUM_CS)
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ret = 1;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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if (cs < SPI2_NUM_CS)
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ret = 1;
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break;
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#endif
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default:
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/* Invalid bus number. Do nothing */
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break;
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}
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return ret;
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}
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}
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void spi_cs_activate(struct spi_slave *slave)
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void spi_cs_activate(struct spi_slave *slave)
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@ -74,6 +74,39 @@ struct davinci_spi_regs {
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/* SPIDEF */
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/* SPIDEF */
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#define SPIDEF_CSDEF0_MASK BIT(0)
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#define SPIDEF_CSDEF0_MASK BIT(0)
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#define SPI0_BUS 0
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#define SPI0_BASE CONFIG_SYS_SPI_BASE
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/*
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* Define default SPI0_NUM_CS as 1 for existing platforms that uses this
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* driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
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* if more than one CS is supported and by defining CONFIG_SYS_SPI0.
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*/
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#ifndef CONFIG_SYS_SPI0
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#define SPI0_NUM_CS 1
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#else
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#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
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#endif
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/*
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* define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
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* CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
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*/
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#ifdef CONFIG_SYS_SPI1
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#define SPI1_BUS 1
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#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
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#define SPI1_BASE CONFIG_SYS_SPI1_BASE
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#endif
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/*
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* define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
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* CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
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*/
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#ifdef CONFIG_SYS_SPI2
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#define SPI2_BUS 2
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#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
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#define SPI2_BASE CONFIG_SYS_SPI2_BASE
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#endif
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struct davinci_spi_slave {
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struct davinci_spi_slave {
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struct spi_slave slave;
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struct spi_slave slave;
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struct davinci_spi_regs *regs;
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struct davinci_spi_regs *regs;
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